Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[1]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[2]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[3]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[4]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[5]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[6]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[7]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[8]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[9]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[10]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[11]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[12]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[13]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[14]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[15]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[16]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[17]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[18]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[19]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[20]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[21]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[22]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[23]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[24]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[25]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[26]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[27]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[28]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[29]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[30]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[31]	12126627	1			T30	545		T31	1549		T32	172

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224717206

1

T30

8713

T31

25023

T32

2915

auto[1]

163334858

1

T30

8727

T31

24545

T32

2589

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312423811

1

T30

17440

T31

49568

T32

5093

auto[1]

75628253

1

T32

411

T35

17111

T36

260

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

290726206

1

T30

17440

T31

49568

T32

4669

auto[1]

97325858

1

T32

835

T35

20220

T36

2555

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4435051	1			T30	274		T31	715		T32	53
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3460220	1			T30	271		T31	834		T32	78
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1192341	1			T35	243		T36	5		T37	35
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1398430	1			T32	23		T35	16		T36	31
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	460226	1			T32	7		T35	325		T36	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1180359	1			T32	11		T35	321		T36	2
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4440287	1			T30	282		T31	715		T32	81
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3455425	1			T30	263		T31	834		T32	48
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1189075	1			T32	18		T35	258		T36	2
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1399160	1			T32	15		T35	12		T36	92
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	463718	1			T32	8		T35	316		T36	31
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1178962	1			T32	2		T35	377		T36	6
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4433448	1			T30	280		T31	734		T32	73
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3469817	1			T30	265		T31	815		T32	74
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1188655	1			T35	324		T36	9		T37	25
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1397063	1			T32	10		T35	20		T36	23
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	460710	1			T32	6		T35	271		T37	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1176934	1			T32	9		T35	320		T37	22
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4425572	1			T30	276		T31	869		T32	49
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3467299	1			T30	269		T31	680		T32	71
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1190599	1			T32	1		T35	255		T36	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1395688	1			T32	19		T35	15		T36	87
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	465874	1			T32	18		T35	318		T36	21
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1181595	1			T32	14		T35	338		T36	7
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4422386	1			T30	277		T31	795		T32	51
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3472508	1			T30	268		T31	754		T32	79
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1191735	1			T32	24		T35	268		T36	5
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1399966	1			T32	16		T35	22		T36	36
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	461095	1			T32	1		T35	307		T36	5
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1178937	1			T32	1		T35	257		T37	20
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4433171	1			T30	276		T31	817		T32	107
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3460349	1			T30	269		T31	732		T32	35
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1184432	1			T32	4		T35	262		T36	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1402112	1			T32	18		T35	6		T36	90
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	464039	1			T32	3		T35	349		T36	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1182524	1			T32	5		T35	320		T36	8
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4423526	1			T30	275		T31	808		T32	57
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3472123	1			T30	270		T31	741		T32	69
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1190266	1			T35	239		T36	4		T37	19
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1401598	1			T32	28		T35	9		T36	83
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	462908	1			T32	17		T35	329		T36	22
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1176206	1			T32	1		T35	304		T36	2
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4425730	1			T30	264		T31	754		T32	79
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3469226	1			T30	281		T31	795		T32	70
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1188020	1			T32	3		T35	210		T37	25
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1402071	1			T32	13		T35	21		T36	100
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	461625	1			T32	2		T35	494		T36	25
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1179955	1			T32	5		T35	282		T36	9
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4431651	1			T30	270		T31	758		T32	60
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3462620	1			T30	275		T31	791		T32	70
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1189727	1			T32	5		T35	234		T36	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1400584	1			T32	18		T35	14		T36	34
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	462200	1			T32	9		T35	390		T36	5
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1179845	1			T32	10		T35	307		T37	27
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4429759	1			T30	252		T31	780		T32	78
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3459850	1			T30	293		T31	769		T32	55
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1190827	1			T32	7		T35	278		T36	5
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1402004	1			T32	15		T35	11		T36	46
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	463829	1			T32	11		T35	354		T36	21
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1180358	1			T32	6		T35	243		T36	4
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4448821	1			T30	276		T31	818		T32	95
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3450805	1			T30	269		T31	731		T32	39
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1189236	1			T32	7		T35	218		T36	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1397239	1			T32	9		T35	23		T36	93
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	462630	1			T32	15		T35	339		T36	24
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1177896	1			T32	7		T35	344		T36	4
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4430301	1			T30	283		T31	799		T32	89
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3466606	1			T30	262		T31	750		T32	39
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1189988	1			T32	1		T35	280		T36	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1401233	1			T32	27		T35	5		T36	85
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	461196	1			T32	12		T35	335		T36	21
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1177303	1			T32	4		T35	243		T37	35
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4436179	1			T30	268		T31	775		T32	52
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3456540	1			T30	277		T31	774		T32	87
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1189940	1			T32	18		T35	300		T36	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1400886	1			T32	11		T35	8		T36	107
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	463227	1			T32	1		T35	308		T36	19
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1179855	1			T32	3		T35	328		T36	2
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4432424	1			T30	283		T31	792		T32	72
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3464270	1			T30	262		T31	757		T32	60
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1187500	1			T32	10		T35	357		T36	6
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1400235	1			T32	22		T35	10		T36	65
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	463985	1			T32	3		T35	307		T36	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1178213	1			T32	5		T35	243		T36	3
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4427769	1			T30	278		T31	798		T32	58
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3462847	1			T30	267		T31	751		T32	70
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1188219	1			T32	7		T35	224		T36	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1405269	1			T32	15		T35	15		T36	65
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	462849	1			T32	12		T35	352		T36	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1179674	1			T32	10		T35	302		T36	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4426766	1			T30	271		T31	871		T32	104
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3464153	1			T30	274		T31	678		T32	49
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1188069	1			T32	13		T35	234		T36	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1398036	1			T32	6		T35	15		T36	46
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	465354	1			T35	430		T36	11		T37	7
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1184249	1			T35	200		T36	4		T37	29
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4427451	1			T30	263		T31	836		T32	59
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3469649	1			T30	282		T31	713		T32	63
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1185229	1			T32	4		T35	272		T36	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1406140	1			T32	16		T35	6		T36	65
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	463372	1			T32	7		T35	306		T36	22
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1174786	1			T32	23		T35	216		T36	4
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4437384	1			T30	260		T31	769		T32	45
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3457498	1			T30	285		T31	780		T32	95
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1183739	1			T32	9		T35	255		T37	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1408533	1			T32	2		T35	10		T36	65
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	462952	1			T32	10		T35	349		T36	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1176521	1			T32	11		T35	209		T36	6
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4432232	1			T30	275		T31	758		T32	54
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3469384	1			T30	270		T31	791		T32	92
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1181404	1			T32	5		T35	244		T36	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1407811	1			T32	8		T35	11		T37	18
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	462714	1			T32	9		T35	368		T40	523
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1173082	1			T32	4		T35	186		T37	17
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4438282	1			T30	271		T31	740		T32	78
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3466278	1			T30	274		T31	809		T32	67
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1187730	1			T32	2		T35	271		T37	25
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1398835	1			T32	9		T35	12		T36	68
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	464204	1			T32	4		T35	331		T36	28
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1171298	1			T32	12		T35	272		T36	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4422399	1			T30	245		T31	823		T32	71
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3474356	1			T30	300		T31	726		T32	75
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1181126	1			T32	3		T35	268		T36	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1410037	1			T32	8		T35	17		T36	51
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	465369	1			T32	6		T35	391		T36	11
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1173340	1			T32	9		T35	248		T36	9
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4435609	1			T30	282		T31	750		T32	75
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3459920	1			T30	263		T31	799		T32	80
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1183554	1			T32	6		T35	249		T36	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1408926	1			T32	8		T35	6		T36	41
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	466371	1			T32	3		T35	365		T36	9
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1172247	1			T35	222		T37	14		T40	5366
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4432549	1			T30	274		T31	737		T32	65
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3476162	1			T30	271		T31	812		T32	77
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1185098	1			T35	308		T36	9		T37	22
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1400976	1			T32	13		T35	13		T36	68
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	460184	1			T32	11		T35	283		T36	17
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1171658	1			T32	6		T35	210		T36	9
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4443628	1			T30	280		T31	731		T32	53
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3461944	1			T30	265		T31	818		T32	77
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1189596	1			T32	4		T35	324		T36	12
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1398054	1			T32	8		T35	9		T36	49
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	462143	1			T32	8		T35	327		T36	14
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1171262	1			T32	22		T35	248		T36	2
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4438556	1			T30	272		T31	786		T32	76
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3465196	1			T30	273		T31	763		T32	79
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1185094	1			T35	273		T36	4		T37	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1406220	1			T32	9		T35	6		T36	35
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	464635	1			T32	6		T35	373		T36	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1166926	1			T32	2		T35	298		T37	7
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4438450	1			T30	274		T31	817		T32	81
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3468898	1			T30	271		T31	732		T32	74
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1186759	1			T32	10		T35	236		T37	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1397995	1			T32	3		T35	11		T36	97
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	461696	1			T32	2		T35	380		T36	26
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1172829	1			T32	2		T35	289		T36	6
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4439781	1			T30	285		T31	756		T32	73
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3460949	1			T30	260		T31	793		T32	78
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1181741	1			T32	5		T35	211		T36	6
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1407027	1			T32	10		T35	20		T36	48
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	465621	1			T32	4		T35	399		T36	16
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1171508	1			T32	2		T35	289		T37	17
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4425818	1			T30	279		T31	765		T32	95
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3474148	1			T30	266		T31	784		T32	45
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1184741	1			T32	14		T35	302		T36	4
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1401812	1			T32	14		T35	15		T36	57
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	464687	1			T32	2		T35	268		T36	14
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1175421	1			T32	2		T35	312		T36	6
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4429611	1			T30	258		T31	800		T32	72
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3467642	1			T30	287		T31	749		T32	75
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1188657	1			T32	11		T35	223		T37	22
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1400616	1			T32	14		T35	11		T36	50
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	464119	1			T35	350		T36	8		T37	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1175982	1			T35	333		T36	4		T37	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4442358	1			T30	274		T31	781		T32	72
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3458942	1			T30	271		T31	768		T32	56
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1185271	1			T32	3		T35	294		T36	11
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1405956	1			T32	27		T35	6		T36	29
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	463757	1			T32	6		T35	298		T36	7
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1170343	1			T32	8		T35	264		T36	2
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4439591	1			T30	263		T31	747		T32	53
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3461756	1			T30	282		T31	802		T32	107
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1187883	1			T32	2		T35	236		T36	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1400501	1			T32	4		T35	11		T36	68
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	463190	1			T32	2		T35	402		T36	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1173706	1			T32	4		T35	221		T36	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4436703	1			T30	273		T31	829		T32	102
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3465433	1			T30	272		T31	720		T32	45
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1183899	1			T32	13		T35	197		T36	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1402800	1			T32	6		T35	18		T36	77
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	463463	1			T32	4		T35	338		T36	26
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1174329	1			T32	2		T35	218		T36	10

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal