Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[1]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[2]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[3]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[4]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[5]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[6]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[7]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[8]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[9]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[10]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[11]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[12]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[13]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[14]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[15]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[16]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[17]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[18]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[19]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[20]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[21]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[22]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[23]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[24]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[25]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[26]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[27]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[28]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[29]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[30]	12126627	1			T30	545		T31	1549		T32	172
bins_for_gpio_bits[31]	12126627	1			T30	545		T31	1549		T32	172

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224717206

1

T30

8713

T31

25023

T32

2915

auto[1]

163334858

1

T30

8727

T31

24545

T32

2589

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

224711156

1

T30

8713

T31

25023

T32

2914

auto[1]

163340908

1

T30

8727

T31

24545

T32

2590

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6812751	1			T30	274		T31	715		T32	76
bins_for_gpio_bits[0]	auto[0]	auto[1]	212877	1			T35	38		T36	1		T37	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	213071	1			T35	38		T36	1		T37	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	4887928	1			T30	271		T31	834		T32	96
bins_for_gpio_bits[1]	auto[0]	auto[0]	6815794	1			T30	282		T31	715		T32	114
bins_for_gpio_bits[1]	auto[0]	auto[1]	212550	1			T35	36		T36	3		T37	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	212728	1			T35	36		T36	3		T37	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	4885555	1			T30	263		T31	834		T32	58
bins_for_gpio_bits[2]	auto[0]	auto[0]	6806453	1			T30	280		T31	734		T32	83
bins_for_gpio_bits[2]	auto[0]	auto[1]	212520	1			T35	40		T37	2		T40	972
bins_for_gpio_bits[2]	auto[1]	auto[0]	212713	1			T35	40		T37	2		T40	978
bins_for_gpio_bits[2]	auto[1]	auto[1]	4894941	1			T30	265		T31	815		T32	89
bins_for_gpio_bits[3]	auto[0]	auto[0]	6798650	1			T30	276		T31	869		T32	69
bins_for_gpio_bits[3]	auto[0]	auto[1]	213009	1			T35	30		T36	3		T37	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	213209	1			T35	30		T36	3		T37	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	4901759	1			T30	269		T31	680		T32	103
bins_for_gpio_bits[4]	auto[0]	auto[0]	6800578	1			T30	277		T31	795		T32	91
bins_for_gpio_bits[4]	auto[0]	auto[1]	213314	1			T35	38		T37	4		T40	966
bins_for_gpio_bits[4]	auto[1]	auto[0]	213509	1			T35	37		T37	4		T40	969
bins_for_gpio_bits[4]	auto[1]	auto[1]	4899226	1			T30	268		T31	754		T32	81
bins_for_gpio_bits[5]	auto[0]	auto[0]	6807329	1			T30	276		T31	817		T32	129
bins_for_gpio_bits[5]	auto[0]	auto[1]	212179	1			T35	40		T36	3		T37	4
bins_for_gpio_bits[5]	auto[1]	auto[0]	212386	1			T35	40		T36	3		T37	4
bins_for_gpio_bits[5]	auto[1]	auto[1]	4894733	1			T30	269		T31	732		T32	43
bins_for_gpio_bits[6]	auto[0]	auto[0]	6803097	1			T30	275		T31	808		T32	85
bins_for_gpio_bits[6]	auto[0]	auto[1]	212049	1			T35	35		T36	1		T37	7
bins_for_gpio_bits[6]	auto[1]	auto[0]	212293	1			T35	34		T36	1		T37	7
bins_for_gpio_bits[6]	auto[1]	auto[1]	4899188	1			T30	270		T31	741		T32	87
bins_for_gpio_bits[7]	auto[0]	auto[0]	6803146	1			T30	264		T31	754		T32	95
bins_for_gpio_bits[7]	auto[0]	auto[1]	212484	1			T35	26		T36	3		T37	4
bins_for_gpio_bits[7]	auto[1]	auto[0]	212675	1			T35	26		T36	3		T37	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	4898322	1			T30	281		T31	795		T32	77
bins_for_gpio_bits[8]	auto[0]	auto[0]	6809346	1			T30	270		T31	758		T32	83
bins_for_gpio_bits[8]	auto[0]	auto[1]	212455	1			T35	36		T37	5		T40	945
bins_for_gpio_bits[8]	auto[1]	auto[0]	212616	1			T35	36		T37	5		T40	948
bins_for_gpio_bits[8]	auto[1]	auto[1]	4892210	1			T30	275		T31	791		T32	89
bins_for_gpio_bits[9]	auto[0]	auto[0]	6809668	1			T30	252		T31	780		T32	100
bins_for_gpio_bits[9]	auto[0]	auto[1]	212730	1			T35	36		T36	1		T37	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	212922	1			T35	36		T36	1		T37	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	4891307	1			T30	293		T31	769		T32	72
bins_for_gpio_bits[10]	auto[0]	auto[0]	6822810	1			T30	276		T31	818		T32	111
bins_for_gpio_bits[10]	auto[0]	auto[1]	212299	1			T35	37		T36	2		T37	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	212486	1			T35	37		T36	2		T37	2
bins_for_gpio_bits[10]	auto[1]	auto[1]	4879032	1			T30	269		T31	731		T32	61
bins_for_gpio_bits[11]	auto[0]	auto[0]	6808294	1			T30	283		T31	799		T32	117
bins_for_gpio_bits[11]	auto[0]	auto[1]	213062	1			T35	36		T37	3		T40	996
bins_for_gpio_bits[11]	auto[1]	auto[0]	213228	1			T35	35		T37	3		T40	1000
bins_for_gpio_bits[11]	auto[1]	auto[1]	4892043	1			T30	262		T31	750		T32	55
bins_for_gpio_bits[12]	auto[0]	auto[0]	6814558	1			T30	268		T31	775		T32	81
bins_for_gpio_bits[12]	auto[0]	auto[1]	212279	1			T35	50		T36	1		T37	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	212447	1			T35	50		T36	1		T37	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	4887343	1			T30	277		T31	774		T32	91
bins_for_gpio_bits[13]	auto[0]	auto[0]	6807622	1			T30	283		T31	792		T32	104
bins_for_gpio_bits[13]	auto[0]	auto[1]	212361	1			T35	43		T36	1		T37	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	212537	1			T35	43		T36	1		T37	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	4894107	1			T30	262		T31	757		T32	68
bins_for_gpio_bits[14]	auto[0]	auto[0]	6808591	1			T30	278		T31	798		T32	80
bins_for_gpio_bits[14]	auto[0]	auto[1]	212498	1			T32	1		T35	28		T36	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	212666	1			T35	28		T36	1		T37	6
bins_for_gpio_bits[14]	auto[1]	auto[1]	4892872	1			T30	267		T31	751		T32	91
bins_for_gpio_bits[15]	auto[0]	auto[0]	6799836	1			T30	271		T31	871		T32	123
bins_for_gpio_bits[15]	auto[0]	auto[1]	212871	1			T35	35		T36	1		T37	4
bins_for_gpio_bits[15]	auto[1]	auto[0]	213035	1			T35	35		T36	1		T37	4
bins_for_gpio_bits[15]	auto[1]	auto[1]	4900885	1			T30	274		T31	678		T32	49
bins_for_gpio_bits[16]	auto[0]	auto[0]	6805578	1			T30	263		T31	836		T32	79
bins_for_gpio_bits[16]	auto[0]	auto[1]	213069	1			T35	39		T36	2		T37	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	213242	1			T35	38		T36	2		T37	7
bins_for_gpio_bits[16]	auto[1]	auto[1]	4894738	1			T30	282		T31	713		T32	93
bins_for_gpio_bits[17]	auto[0]	auto[0]	6816691	1			T30	260		T31	769		T32	55
bins_for_gpio_bits[17]	auto[0]	auto[1]	212747	1			T35	40		T36	2		T37	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	212965	1			T32	1		T35	39		T36	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	4884224	1			T30	285		T31	780		T32	116
bins_for_gpio_bits[18]	auto[0]	auto[0]	6808768	1			T30	275		T31	758		T32	67
bins_for_gpio_bits[18]	auto[0]	auto[1]	212488	1			T35	33		T37	3		T40	988
bins_for_gpio_bits[18]	auto[1]	auto[0]	212679	1			T35	32		T37	3		T40	993
bins_for_gpio_bits[18]	auto[1]	auto[1]	4892692	1			T30	270		T31	791		T32	105
bins_for_gpio_bits[19]	auto[0]	auto[0]	6812359	1			T30	271		T31	740		T32	89
bins_for_gpio_bits[19]	auto[0]	auto[1]	212297	1			T35	40		T36	1		T37	4
bins_for_gpio_bits[19]	auto[1]	auto[0]	212488	1			T35	40		T36	1		T37	4
bins_for_gpio_bits[19]	auto[1]	auto[1]	4889483	1			T30	274		T31	809		T32	83
bins_for_gpio_bits[20]	auto[0]	auto[0]	6800688	1			T30	245		T31	823		T32	82
bins_for_gpio_bits[20]	auto[0]	auto[1]	212683	1			T35	36		T36	2		T37	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	212874	1			T35	36		T36	2		T37	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	4900382	1			T30	300		T31	726		T32	90
bins_for_gpio_bits[21]	auto[0]	auto[0]	6815432	1			T30	282		T31	750		T32	89
bins_for_gpio_bits[21]	auto[0]	auto[1]	212472	1			T35	34		T37	3		T40	971
bins_for_gpio_bits[21]	auto[1]	auto[0]	212657	1			T35	34		T37	3		T40	973
bins_for_gpio_bits[21]	auto[1]	auto[1]	4886066	1			T30	263		T31	799		T32	83
bins_for_gpio_bits[22]	auto[0]	auto[0]	6806179	1			T30	274		T31	737		T32	78
bins_for_gpio_bits[22]	auto[0]	auto[1]	212241	1			T35	42		T36	4		T37	3
bins_for_gpio_bits[22]	auto[1]	auto[0]	212444	1			T35	42		T36	4		T37	3
bins_for_gpio_bits[22]	auto[1]	auto[1]	4895763	1			T30	271		T31	812		T32	94
bins_for_gpio_bits[23]	auto[0]	auto[0]	6818470	1			T30	280		T31	731		T32	64
bins_for_gpio_bits[23]	auto[0]	auto[1]	212595	1			T32	1		T35	49		T36	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	212808	1			T32	1		T35	49		T36	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	4882754	1			T30	265		T31	818		T32	106
bins_for_gpio_bits[24]	auto[0]	auto[0]	6817584	1			T30	272		T31	786		T32	84
bins_for_gpio_bits[24]	auto[0]	auto[1]	212091	1			T35	34		T37	2		T40	996
bins_for_gpio_bits[24]	auto[1]	auto[0]	212286	1			T32	1		T35	34		T37	2
bins_for_gpio_bits[24]	auto[1]	auto[1]	4884666	1			T30	273		T31	763		T32	87
bins_for_gpio_bits[25]	auto[0]	auto[0]	6810441	1			T30	274		T31	817		T32	94
bins_for_gpio_bits[25]	auto[0]	auto[1]	212612	1			T35	36		T36	2		T37	3
bins_for_gpio_bits[25]	auto[1]	auto[0]	212763	1			T35	36		T36	2		T37	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	4890811	1			T30	271		T31	732		T32	78
bins_for_gpio_bits[26]	auto[0]	auto[0]	6816137	1			T30	285		T31	756		T32	88
bins_for_gpio_bits[26]	auto[0]	auto[1]	212194	1			T35	38		T37	5		T40	966
bins_for_gpio_bits[26]	auto[1]	auto[0]	212412	1			T35	37		T37	5		T40	969
bins_for_gpio_bits[26]	auto[1]	auto[1]	4885884	1			T30	260		T31	793		T32	84
bins_for_gpio_bits[27]	auto[0]	auto[0]	6799830	1			T30	279		T31	765		T32	123
bins_for_gpio_bits[27]	auto[0]	auto[1]	212352	1			T35	48		T36	2		T37	3
bins_for_gpio_bits[27]	auto[1]	auto[0]	212541	1			T35	48		T36	2		T37	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	4901904	1			T30	266		T31	784		T32	49
bins_for_gpio_bits[28]	auto[0]	auto[0]	6806213	1			T30	258		T31	800		T32	97
bins_for_gpio_bits[28]	auto[0]	auto[1]	212503	1			T35	29		T36	2		T37	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	212671	1			T35	29		T36	2		T37	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	4895240	1			T30	287		T31	749		T32	75
bins_for_gpio_bits[29]	auto[0]	auto[0]	6820783	1			T30	274		T31	781		T32	102
bins_for_gpio_bits[29]	auto[0]	auto[1]	212583	1			T35	45		T36	1		T37	3
bins_for_gpio_bits[29]	auto[1]	auto[0]	212802	1			T35	45		T36	1		T37	3
bins_for_gpio_bits[29]	auto[1]	auto[1]	4880459	1			T30	271		T31	768		T32	70
bins_for_gpio_bits[30]	auto[0]	auto[0]	6815171	1			T30	263		T31	747		T32	59
bins_for_gpio_bits[30]	auto[0]	auto[1]	212627	1			T35	38		T36	2		T37	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	212804	1			T35	37		T36	2		T37	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	4886025	1			T30	282		T31	802		T32	113
bins_for_gpio_bits[31]	auto[0]	auto[0]	6810669	1			T30	273		T31	829		T32	121
bins_for_gpio_bits[31]	auto[0]	auto[1]	212549	1			T35	35		T36	4		T37	2
bins_for_gpio_bits[31]	auto[1]	auto[0]	212733	1			T35	35		T36	4		T37	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	4890676	1			T30	272		T31	720		T32	51