Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7200479 |
1 |
|
|
T30 |
288 |
|
T31 |
1549 |
|
T32 |
119 |
| auto[1] |
5120513 |
1 |
|
|
T30 |
413 |
|
T32 |
25 |
|
T33 |
327 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659524 |
1 |
|
|
T30 |
647 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
661468 |
1 |
|
|
T30 |
54 |
|
T33 |
85 |
|
T35 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7188257 |
1 |
|
|
T30 |
428 |
|
T31 |
1549 |
|
T32 |
75 |
| auto[1] |
5132735 |
1 |
|
|
T30 |
273 |
|
T32 |
69 |
|
T33 |
490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2242968 |
1 |
|
|
T30 |
145 |
|
T32 |
61 |
|
T33 |
221 |
| auto[1] |
auto[0] |
auto[1] |
333032 |
1 |
|
|
T30 |
39 |
|
T33 |
46 |
|
T35 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2228299 |
1 |
|
|
T30 |
74 |
|
T32 |
8 |
|
T33 |
184 |
| auto[1] |
auto[1] |
auto[1] |
328436 |
1 |
|
|
T30 |
15 |
|
T33 |
39 |
|
T35 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7188715 |
1 |
|
|
T30 |
203 |
|
T31 |
1549 |
|
T32 |
107 |
| auto[1] |
5132277 |
1 |
|
|
T30 |
498 |
|
T32 |
37 |
|
T33 |
393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11657235 |
1 |
|
|
T30 |
628 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
663757 |
1 |
|
|
T30 |
73 |
|
T32 |
1 |
|
T33 |
89 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7177430 |
1 |
|
|
T30 |
297 |
|
T31 |
1549 |
|
T32 |
83 |
| auto[1] |
5143562 |
1 |
|
|
T30 |
404 |
|
T32 |
61 |
|
T33 |
444 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2230478 |
1 |
|
|
T30 |
111 |
|
T32 |
35 |
|
T33 |
206 |
| auto[1] |
auto[0] |
auto[1] |
329924 |
1 |
|
|
T30 |
28 |
|
T33 |
47 |
|
T35 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2249327 |
1 |
|
|
T30 |
220 |
|
T32 |
25 |
|
T33 |
149 |
| auto[1] |
auto[1] |
auto[1] |
333833 |
1 |
|
|
T30 |
45 |
|
T32 |
1 |
|
T33 |
42 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7194385 |
1 |
|
|
T30 |
330 |
|
T31 |
1549 |
|
T32 |
130 |
| auto[1] |
5126607 |
1 |
|
|
T30 |
371 |
|
T32 |
14 |
|
T33 |
484 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661005 |
1 |
|
|
T30 |
615 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
659987 |
1 |
|
|
T30 |
86 |
|
T32 |
1 |
|
T33 |
113 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7185997 |
1 |
|
|
T30 |
282 |
|
T31 |
1549 |
|
T32 |
95 |
| auto[1] |
5134995 |
1 |
|
|
T30 |
419 |
|
T32 |
49 |
|
T33 |
565 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2250982 |
1 |
|
|
T30 |
157 |
|
T32 |
42 |
|
T33 |
254 |
| auto[1] |
auto[0] |
auto[1] |
333032 |
1 |
|
|
T30 |
39 |
|
T32 |
1 |
|
T33 |
63 |
| auto[1] |
auto[1] |
auto[0] |
2224026 |
1 |
|
|
T30 |
176 |
|
T32 |
6 |
|
T33 |
198 |
| auto[1] |
auto[1] |
auto[1] |
326955 |
1 |
|
|
T30 |
47 |
|
T33 |
50 |
|
T35 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7209293 |
1 |
|
|
T30 |
226 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5111699 |
1 |
|
|
T30 |
475 |
|
T32 |
46 |
|
T33 |
351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660403 |
1 |
|
|
T30 |
626 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
660589 |
1 |
|
|
T30 |
75 |
|
T32 |
1 |
|
T33 |
79 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7179152 |
1 |
|
|
T30 |
331 |
|
T31 |
1549 |
|
T32 |
103 |
| auto[1] |
5141840 |
1 |
|
|
T30 |
370 |
|
T32 |
41 |
|
T33 |
385 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2244186 |
1 |
|
|
T30 |
149 |
|
T32 |
20 |
|
T33 |
203 |
| auto[1] |
auto[0] |
auto[1] |
330296 |
1 |
|
|
T30 |
41 |
|
T33 |
57 |
|
T35 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2237065 |
1 |
|
|
T30 |
146 |
|
T32 |
20 |
|
T33 |
103 |
| auto[1] |
auto[1] |
auto[1] |
330293 |
1 |
|
|
T30 |
34 |
|
T32 |
1 |
|
T33 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7177269 |
1 |
|
|
T30 |
384 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
5143723 |
1 |
|
|
T30 |
317 |
|
T32 |
33 |
|
T33 |
461 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661960 |
1 |
|
|
T30 |
637 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
659032 |
1 |
|
|
T30 |
64 |
|
T33 |
74 |
|
T35 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7192044 |
1 |
|
|
T30 |
367 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5128948 |
1 |
|
|
T30 |
334 |
|
T32 |
53 |
|
T33 |
418 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2235674 |
1 |
|
|
T30 |
125 |
|
T32 |
47 |
|
T33 |
120 |
| auto[1] |
auto[0] |
auto[1] |
329303 |
1 |
|
|
T30 |
27 |
|
T33 |
22 |
|
T35 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2234242 |
1 |
|
|
T30 |
145 |
|
T32 |
6 |
|
T33 |
224 |
| auto[1] |
auto[1] |
auto[1] |
329729 |
1 |
|
|
T30 |
37 |
|
T33 |
52 |
|
T35 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196044 |
1 |
|
|
T30 |
365 |
|
T31 |
1549 |
|
T32 |
92 |
| auto[1] |
5124948 |
1 |
|
|
T30 |
336 |
|
T32 |
52 |
|
T33 |
292 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663004 |
1 |
|
|
T30 |
626 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
657988 |
1 |
|
|
T30 |
75 |
|
T33 |
115 |
|
T35 |
31 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198978 |
1 |
|
|
T30 |
339 |
|
T31 |
1549 |
|
T32 |
92 |
| auto[1] |
5122014 |
1 |
|
|
T30 |
362 |
|
T32 |
52 |
|
T33 |
548 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2231491 |
1 |
|
|
T30 |
157 |
|
T32 |
36 |
|
T33 |
314 |
| auto[1] |
auto[0] |
auto[1] |
328575 |
1 |
|
|
T30 |
46 |
|
T33 |
91 |
|
T35 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2232535 |
1 |
|
|
T30 |
130 |
|
T32 |
16 |
|
T33 |
119 |
| auto[1] |
auto[1] |
auto[1] |
329413 |
1 |
|
|
T30 |
29 |
|
T33 |
24 |
|
T35 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7195735 |
1 |
|
|
T30 |
179 |
|
T31 |
1549 |
|
T32 |
87 |
| auto[1] |
5125257 |
1 |
|
|
T30 |
522 |
|
T32 |
57 |
|
T33 |
490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663937 |
1 |
|
|
T30 |
615 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
657055 |
1 |
|
|
T30 |
86 |
|
T32 |
1 |
|
T33 |
59 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7205134 |
1 |
|
|
T30 |
240 |
|
T31 |
1549 |
|
T32 |
105 |
| auto[1] |
5115858 |
1 |
|
|
T30 |
461 |
|
T32 |
39 |
|
T33 |
320 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2220913 |
1 |
|
|
T30 |
69 |
|
T32 |
21 |
|
T33 |
112 |
| auto[1] |
auto[0] |
auto[1] |
326734 |
1 |
|
|
T30 |
14 |
|
T32 |
1 |
|
T33 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2237890 |
1 |
|
|
T30 |
306 |
|
T32 |
17 |
|
T33 |
149 |
| auto[1] |
auto[1] |
auto[1] |
330321 |
1 |
|
|
T30 |
72 |
|
T33 |
41 |
|
T35 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7199085 |
1 |
|
|
T30 |
330 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5121907 |
1 |
|
|
T30 |
371 |
|
T32 |
38 |
|
T33 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661051 |
1 |
|
|
T30 |
597 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
659941 |
1 |
|
|
T30 |
104 |
|
T33 |
63 |
|
T35 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7192474 |
1 |
|
|
T30 |
190 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5128518 |
1 |
|
|
T30 |
511 |
|
T32 |
38 |
|
T33 |
344 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2236870 |
1 |
|
|
T30 |
190 |
|
T32 |
35 |
|
T33 |
146 |
| auto[1] |
auto[0] |
auto[1] |
330132 |
1 |
|
|
T30 |
55 |
|
T33 |
36 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2231707 |
1 |
|
|
T30 |
217 |
|
T32 |
3 |
|
T33 |
135 |
| auto[1] |
auto[1] |
auto[1] |
329809 |
1 |
|
|
T30 |
49 |
|
T33 |
27 |
|
T35 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7189149 |
1 |
|
|
T30 |
338 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5131843 |
1 |
|
|
T30 |
363 |
|
T32 |
38 |
|
T33 |
314 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659404 |
1 |
|
|
T30 |
621 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
661588 |
1 |
|
|
T30 |
80 |
|
T32 |
1 |
|
T33 |
68 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7182088 |
1 |
|
|
T30 |
290 |
|
T31 |
1549 |
|
T32 |
85 |
| auto[1] |
5138904 |
1 |
|
|
T30 |
411 |
|
T32 |
59 |
|
T33 |
318 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240779 |
1 |
|
|
T30 |
174 |
|
T32 |
40 |
|
T33 |
163 |
| auto[1] |
auto[0] |
auto[1] |
330542 |
1 |
|
|
T30 |
40 |
|
T32 |
1 |
|
T33 |
45 |
| auto[1] |
auto[1] |
auto[0] |
2236537 |
1 |
|
|
T30 |
157 |
|
T32 |
18 |
|
T33 |
87 |
| auto[1] |
auto[1] |
auto[1] |
331046 |
1 |
|
|
T30 |
40 |
|
T33 |
23 |
|
T35 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7186173 |
1 |
|
|
T30 |
263 |
|
T31 |
1549 |
|
T32 |
117 |
| auto[1] |
5134819 |
1 |
|
|
T30 |
438 |
|
T32 |
27 |
|
T33 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662079 |
1 |
|
|
T30 |
649 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
658913 |
1 |
|
|
T30 |
52 |
|
T32 |
1 |
|
T33 |
65 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7197389 |
1 |
|
|
T30 |
450 |
|
T31 |
1549 |
|
T32 |
96 |
| auto[1] |
5123603 |
1 |
|
|
T30 |
251 |
|
T32 |
48 |
|
T33 |
383 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2245562 |
1 |
|
|
T30 |
93 |
|
T32 |
27 |
|
T33 |
142 |
| auto[1] |
auto[0] |
auto[1] |
331308 |
1 |
|
|
T30 |
24 |
|
T33 |
28 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2219128 |
1 |
|
|
T30 |
106 |
|
T32 |
20 |
|
T33 |
176 |
| auto[1] |
auto[1] |
auto[1] |
327605 |
1 |
|
|
T30 |
28 |
|
T32 |
1 |
|
T33 |
37 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7176569 |
1 |
|
|
T30 |
244 |
|
T31 |
1549 |
|
T32 |
93 |
| auto[1] |
5144423 |
1 |
|
|
T30 |
457 |
|
T32 |
51 |
|
T33 |
391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659930 |
1 |
|
|
T30 |
659 |
|
T31 |
1549 |
|
T32 |
142 |
| auto[1] |
661062 |
1 |
|
|
T30 |
42 |
|
T32 |
2 |
|
T33 |
55 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7171726 |
1 |
|
|
T30 |
507 |
|
T31 |
1549 |
|
T32 |
92 |
| auto[1] |
5149266 |
1 |
|
|
T30 |
194 |
|
T32 |
52 |
|
T33 |
297 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233322 |
1 |
|
|
T30 |
88 |
|
T32 |
19 |
|
T33 |
160 |
| auto[1] |
auto[0] |
auto[1] |
328815 |
1 |
|
|
T30 |
25 |
|
T33 |
38 |
|
T35 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2254882 |
1 |
|
|
T30 |
64 |
|
T32 |
31 |
|
T33 |
82 |
| auto[1] |
auto[1] |
auto[1] |
332247 |
1 |
|
|
T30 |
17 |
|
T32 |
2 |
|
T33 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7175014 |
1 |
|
|
T30 |
267 |
|
T31 |
1549 |
|
T32 |
109 |
| auto[1] |
5145978 |
1 |
|
|
T30 |
434 |
|
T32 |
35 |
|
T33 |
530 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659890 |
1 |
|
|
T30 |
648 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
661102 |
1 |
|
|
T30 |
53 |
|
T32 |
1 |
|
T33 |
91 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7174326 |
1 |
|
|
T30 |
445 |
|
T31 |
1549 |
|
T32 |
83 |
| auto[1] |
5146666 |
1 |
|
|
T30 |
256 |
|
T32 |
61 |
|
T33 |
467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233048 |
1 |
|
|
T30 |
144 |
|
T32 |
40 |
|
T33 |
161 |
| auto[1] |
auto[0] |
auto[1] |
328395 |
1 |
|
|
T30 |
35 |
|
T33 |
38 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2252516 |
1 |
|
|
T30 |
59 |
|
T32 |
20 |
|
T33 |
215 |
| auto[1] |
auto[1] |
auto[1] |
332707 |
1 |
|
|
T30 |
18 |
|
T32 |
1 |
|
T33 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7172659 |
1 |
|
|
T30 |
521 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
5148333 |
1 |
|
|
T30 |
180 |
|
T32 |
33 |
|
T33 |
343 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664616 |
1 |
|
|
T30 |
628 |
|
T31 |
1549 |
|
T32 |
141 |
| auto[1] |
656376 |
1 |
|
|
T30 |
73 |
|
T32 |
3 |
|
T33 |
121 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7202334 |
1 |
|
|
T30 |
307 |
|
T31 |
1549 |
|
T32 |
82 |
| auto[1] |
5118658 |
1 |
|
|
T30 |
394 |
|
T32 |
62 |
|
T33 |
608 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2226072 |
1 |
|
|
T30 |
245 |
|
T32 |
36 |
|
T33 |
254 |
| auto[1] |
auto[0] |
auto[1] |
327357 |
1 |
|
|
T30 |
56 |
|
T32 |
3 |
|
T33 |
60 |
| auto[1] |
auto[1] |
auto[0] |
2236210 |
1 |
|
|
T30 |
76 |
|
T32 |
23 |
|
T33 |
233 |
| auto[1] |
auto[1] |
auto[1] |
329019 |
1 |
|
|
T30 |
17 |
|
T33 |
61 |
|
T35 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7233040 |
1 |
|
|
T30 |
372 |
|
T31 |
1549 |
|
T32 |
82 |
| auto[1] |
5087952 |
1 |
|
|
T30 |
329 |
|
T32 |
62 |
|
T33 |
361 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661295 |
1 |
|
|
T30 |
606 |
|
T31 |
1549 |
|
T32 |
142 |
| auto[1] |
659697 |
1 |
|
|
T30 |
95 |
|
T32 |
2 |
|
T33 |
102 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7195419 |
1 |
|
|
T30 |
238 |
|
T31 |
1549 |
|
T32 |
108 |
| auto[1] |
5125573 |
1 |
|
|
T30 |
463 |
|
T32 |
36 |
|
T33 |
512 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2260243 |
1 |
|
|
T30 |
192 |
|
T32 |
26 |
|
T33 |
225 |
| auto[1] |
auto[0] |
auto[1] |
335328 |
1 |
|
|
T30 |
51 |
|
T32 |
2 |
|
T33 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2205633 |
1 |
|
|
T30 |
176 |
|
T32 |
8 |
|
T33 |
185 |
| auto[1] |
auto[1] |
auto[1] |
324369 |
1 |
|
|
T30 |
44 |
|
T33 |
43 |
|
T35 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7211377 |
1 |
|
|
T30 |
306 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5109615 |
1 |
|
|
T30 |
395 |
|
T32 |
46 |
|
T33 |
346 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11658190 |
1 |
|
|
T30 |
630 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
662802 |
1 |
|
|
T30 |
71 |
|
T32 |
1 |
|
T33 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7163840 |
1 |
|
|
T30 |
326 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5157152 |
1 |
|
|
T30 |
375 |
|
T32 |
53 |
|
T33 |
634 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2261278 |
1 |
|
|
T30 |
132 |
|
T32 |
30 |
|
T33 |
284 |
| auto[1] |
auto[0] |
auto[1] |
334011 |
1 |
|
|
T30 |
30 |
|
T33 |
80 |
|
T35 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2233072 |
1 |
|
|
T30 |
172 |
|
T32 |
22 |
|
T33 |
216 |
| auto[1] |
auto[1] |
auto[1] |
328791 |
1 |
|
|
T30 |
41 |
|
T32 |
1 |
|
T33 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7202985 |
1 |
|
|
T30 |
536 |
|
T31 |
1549 |
|
T32 |
89 |
| auto[1] |
5118007 |
1 |
|
|
T30 |
165 |
|
T32 |
55 |
|
T33 |
402 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662184 |
1 |
|
|
T30 |
626 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
658808 |
1 |
|
|
T30 |
75 |
|
T33 |
99 |
|
T35 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7195189 |
1 |
|
|
T30 |
306 |
|
T31 |
1549 |
|
T32 |
87 |
| auto[1] |
5125803 |
1 |
|
|
T30 |
395 |
|
T32 |
57 |
|
T33 |
533 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243256 |
1 |
|
|
T30 |
225 |
|
T32 |
34 |
|
T33 |
231 |
| auto[1] |
auto[0] |
auto[1] |
330786 |
1 |
|
|
T30 |
54 |
|
T33 |
55 |
|
T35 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2223739 |
1 |
|
|
T30 |
95 |
|
T32 |
23 |
|
T33 |
203 |
| auto[1] |
auto[1] |
auto[1] |
328022 |
1 |
|
|
T30 |
21 |
|
T33 |
44 |
|
T35 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198594 |
1 |
|
|
T30 |
194 |
|
T31 |
1549 |
|
T32 |
93 |
| auto[1] |
5122398 |
1 |
|
|
T30 |
507 |
|
T32 |
51 |
|
T33 |
468 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660298 |
1 |
|
|
T30 |
654 |
|
T31 |
1549 |
|
T32 |
142 |
| auto[1] |
660694 |
1 |
|
|
T30 |
47 |
|
T32 |
2 |
|
T33 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7172585 |
1 |
|
|
T30 |
465 |
|
T31 |
1549 |
|
T32 |
80 |
| auto[1] |
5148407 |
1 |
|
|
T30 |
236 |
|
T32 |
64 |
|
T33 |
192 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2237802 |
1 |
|
|
T30 |
57 |
|
T32 |
31 |
|
T33 |
64 |
| auto[1] |
auto[0] |
auto[1] |
328840 |
1 |
|
|
T30 |
12 |
|
T32 |
1 |
|
T33 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2249911 |
1 |
|
|
T30 |
132 |
|
T32 |
31 |
|
T33 |
94 |
| auto[1] |
auto[1] |
auto[1] |
331854 |
1 |
|
|
T30 |
35 |
|
T32 |
1 |
|
T33 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7187922 |
1 |
|
|
T30 |
281 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5133070 |
1 |
|
|
T30 |
420 |
|
T32 |
53 |
|
T33 |
647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11666695 |
1 |
|
|
T30 |
660 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
654297 |
1 |
|
|
T30 |
41 |
|
T33 |
61 |
|
T35 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7215270 |
1 |
|
|
T30 |
487 |
|
T31 |
1549 |
|
T32 |
112 |
| auto[1] |
5105722 |
1 |
|
|
T30 |
214 |
|
T32 |
32 |
|
T33 |
284 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2236243 |
1 |
|
|
T30 |
97 |
|
T32 |
17 |
|
T33 |
83 |
| auto[1] |
auto[0] |
auto[1] |
329576 |
1 |
|
|
T30 |
24 |
|
T33 |
23 |
|
T35 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2215182 |
1 |
|
|
T30 |
76 |
|
T32 |
15 |
|
T33 |
140 |
| auto[1] |
auto[1] |
auto[1] |
324721 |
1 |
|
|
T30 |
17 |
|
T33 |
38 |
|
T35 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7183052 |
1 |
|
|
T30 |
181 |
|
T31 |
1549 |
|
T32 |
108 |
| auto[1] |
5137940 |
1 |
|
|
T30 |
520 |
|
T32 |
36 |
|
T33 |
281 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11659663 |
1 |
|
|
T30 |
613 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
661329 |
1 |
|
|
T30 |
88 |
|
T32 |
1 |
|
T33 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7186067 |
1 |
|
|
T30 |
323 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5134925 |
1 |
|
|
T30 |
378 |
|
T32 |
53 |
|
T33 |
311 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233950 |
1 |
|
|
T30 |
83 |
|
T32 |
41 |
|
T33 |
180 |
| auto[1] |
auto[0] |
auto[1] |
329297 |
1 |
|
|
T30 |
25 |
|
T33 |
39 |
|
T35 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2239646 |
1 |
|
|
T30 |
207 |
|
T32 |
11 |
|
T33 |
75 |
| auto[1] |
auto[1] |
auto[1] |
332032 |
1 |
|
|
T30 |
63 |
|
T32 |
1 |
|
T33 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7180433 |
1 |
|
|
T30 |
256 |
|
T31 |
1549 |
|
T32 |
101 |
| auto[1] |
5140559 |
1 |
|
|
T30 |
445 |
|
T32 |
43 |
|
T33 |
436 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663042 |
1 |
|
|
T30 |
615 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
657950 |
1 |
|
|
T30 |
86 |
|
T32 |
1 |
|
T33 |
93 |