Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7181196 |
1 |
|
|
T30 |
397 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5139796 |
1 |
|
|
T30 |
304 |
|
T32 |
38 |
|
T33 |
231 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660256 |
1 |
|
|
T30 |
639 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
660736 |
1 |
|
|
T30 |
62 |
|
T32 |
1 |
|
T33 |
64 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7183797 |
1 |
|
|
T30 |
384 |
|
T31 |
1549 |
|
T32 |
90 |
| auto[1] |
5137195 |
1 |
|
|
T30 |
317 |
|
T32 |
54 |
|
T33 |
339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2235800 |
1 |
|
|
T30 |
131 |
|
T32 |
42 |
|
T33 |
196 |
| auto[1] |
auto[0] |
auto[1] |
328997 |
1 |
|
|
T30 |
33 |
|
T32 |
1 |
|
T33 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2240659 |
1 |
|
|
T30 |
124 |
|
T32 |
11 |
|
T33 |
79 |
| auto[1] |
auto[1] |
auto[1] |
331739 |
1 |
|
|
T30 |
29 |
|
T33 |
18 |
|
T35 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |