Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7191635 |
1 |
|
|
T30 |
270 |
|
T31 |
1549 |
|
T32 |
99 |
| auto[1] |
5129357 |
1 |
|
|
T30 |
431 |
|
T32 |
45 |
|
T33 |
378 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11660864 |
1 |
|
|
T30 |
645 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
660128 |
1 |
|
|
T30 |
56 |
|
T32 |
1 |
|
T33 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7189777 |
1 |
|
|
T30 |
418 |
|
T31 |
1549 |
|
T32 |
117 |
| auto[1] |
5131215 |
1 |
|
|
T30 |
283 |
|
T32 |
27 |
|
T33 |
414 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2237454 |
1 |
|
|
T30 |
67 |
|
T32 |
19 |
|
T33 |
210 |
| auto[1] |
auto[0] |
auto[1] |
329283 |
1 |
|
|
T30 |
12 |
|
T32 |
1 |
|
T33 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2233633 |
1 |
|
|
T30 |
160 |
|
T32 |
7 |
|
T33 |
118 |
| auto[1] |
auto[1] |
auto[1] |
330845 |
1 |
|
|
T30 |
44 |
|
T33 |
32 |
|
T35 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |