Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7176840 |
1 |
|
|
T30 |
348 |
|
T31 |
1549 |
|
T32 |
101 |
| auto[1] |
5144152 |
1 |
|
|
T30 |
353 |
|
T32 |
43 |
|
T33 |
340 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11658871 |
1 |
|
|
T30 |
605 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
662121 |
1 |
|
|
T30 |
96 |
|
T33 |
57 |
|
T35 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7173954 |
1 |
|
|
T30 |
216 |
|
T31 |
1549 |
|
T32 |
100 |
| auto[1] |
5147038 |
1 |
|
|
T30 |
485 |
|
T32 |
44 |
|
T33 |
311 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240296 |
1 |
|
|
T30 |
120 |
|
T32 |
23 |
|
T33 |
117 |
| auto[1] |
auto[0] |
auto[1] |
330152 |
1 |
|
|
T30 |
33 |
|
T33 |
23 |
|
T35 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2244621 |
1 |
|
|
T30 |
269 |
|
T32 |
21 |
|
T33 |
137 |
| auto[1] |
auto[1] |
auto[1] |
331969 |
1 |
|
|
T30 |
63 |
|
T33 |
34 |
|
T35 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |