Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7189881 |
1 |
|
|
T30 |
359 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5131111 |
1 |
|
|
T30 |
342 |
|
T32 |
46 |
|
T33 |
673 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11664888 |
1 |
|
|
T30 |
592 |
|
T31 |
1549 |
|
T32 |
142 |
| auto[1] |
656104 |
1 |
|
|
T30 |
109 |
|
T32 |
2 |
|
T33 |
88 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7212522 |
1 |
|
|
T30 |
151 |
|
T31 |
1549 |
|
T32 |
86 |
| auto[1] |
5108470 |
1 |
|
|
T30 |
550 |
|
T32 |
58 |
|
T33 |
450 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2224619 |
1 |
|
|
T30 |
203 |
|
T32 |
35 |
|
T33 |
119 |
| auto[1] |
auto[0] |
auto[1] |
327887 |
1 |
|
|
T30 |
47 |
|
T33 |
33 |
|
T35 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2227747 |
1 |
|
|
T30 |
238 |
|
T32 |
21 |
|
T33 |
243 |
| auto[1] |
auto[1] |
auto[1] |
328217 |
1 |
|
|
T30 |
62 |
|
T32 |
2 |
|
T33 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |