Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7186744 |
1 |
|
|
T30 |
362 |
|
T31 |
1549 |
|
T32 |
100 |
| auto[1] |
5134248 |
1 |
|
|
T30 |
339 |
|
T32 |
44 |
|
T33 |
562 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11656729 |
1 |
|
|
T30 |
621 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
664263 |
1 |
|
|
T30 |
80 |
|
T32 |
1 |
|
T33 |
98 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7165848 |
1 |
|
|
T30 |
307 |
|
T31 |
1549 |
|
T32 |
96 |
| auto[1] |
5155144 |
1 |
|
|
T30 |
394 |
|
T32 |
48 |
|
T33 |
521 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2245449 |
1 |
|
|
T30 |
197 |
|
T32 |
39 |
|
T33 |
160 |
| auto[1] |
auto[0] |
auto[1] |
331314 |
1 |
|
|
T30 |
46 |
|
T33 |
41 |
|
T35 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2245432 |
1 |
|
|
T30 |
117 |
|
T32 |
8 |
|
T33 |
263 |
| auto[1] |
auto[1] |
auto[1] |
332949 |
1 |
|
|
T30 |
34 |
|
T32 |
1 |
|
T33 |
57 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |