Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7200479 |
1 |
|
|
T30 |
288 |
|
T31 |
1549 |
|
T32 |
119 |
| auto[1] |
5120513 |
1 |
|
|
T30 |
413 |
|
T32 |
25 |
|
T33 |
327 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10132784 |
1 |
|
|
T30 |
550 |
|
T31 |
1549 |
|
T32 |
119 |
| auto[1] |
2188208 |
1 |
|
|
T30 |
151 |
|
T32 |
25 |
|
T33 |
221 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7191192 |
1 |
|
|
T30 |
363 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5129800 |
1 |
|
|
T30 |
338 |
|
T32 |
53 |
|
T33 |
449 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1478069 |
1 |
|
|
T30 |
53 |
|
T32 |
28 |
|
T33 |
120 |
| auto[1] |
auto[0] |
auto[1] |
1098679 |
1 |
|
|
T30 |
50 |
|
T32 |
15 |
|
T33 |
134 |
| auto[1] |
auto[1] |
auto[0] |
1463523 |
1 |
|
|
T30 |
134 |
|
T33 |
108 |
|
T35 |
118 |
| auto[1] |
auto[1] |
auto[1] |
1089529 |
1 |
|
|
T30 |
101 |
|
T32 |
10 |
|
T33 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |