Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7188715 |
1 |
|
|
T30 |
203 |
|
T31 |
1549 |
|
T32 |
107 |
| auto[1] |
5132277 |
1 |
|
|
T30 |
498 |
|
T32 |
37 |
|
T33 |
393 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10123877 |
1 |
|
|
T30 |
613 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
2197115 |
1 |
|
|
T30 |
88 |
|
T32 |
33 |
|
T33 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7165119 |
1 |
|
|
T30 |
505 |
|
T31 |
1549 |
|
T32 |
95 |
| auto[1] |
5155873 |
1 |
|
|
T30 |
196 |
|
T32 |
49 |
|
T33 |
284 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1476315 |
1 |
|
|
T30 |
51 |
|
T32 |
12 |
|
T33 |
86 |
| auto[1] |
auto[0] |
auto[1] |
1097391 |
1 |
|
|
T30 |
25 |
|
T32 |
19 |
|
T33 |
68 |
| auto[1] |
auto[1] |
auto[0] |
1482443 |
1 |
|
|
T30 |
57 |
|
T32 |
4 |
|
T33 |
64 |
| auto[1] |
auto[1] |
auto[1] |
1099724 |
1 |
|
|
T30 |
63 |
|
T32 |
14 |
|
T33 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |