Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7194385 |
1 |
|
|
T30 |
330 |
|
T31 |
1549 |
|
T32 |
130 |
| auto[1] |
5126607 |
1 |
|
|
T30 |
371 |
|
T32 |
14 |
|
T33 |
484 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10139382 |
1 |
|
|
T30 |
560 |
|
T31 |
1549 |
|
T32 |
130 |
| auto[1] |
2181610 |
1 |
|
|
T30 |
141 |
|
T32 |
14 |
|
T33 |
182 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196527 |
1 |
|
|
T30 |
434 |
|
T31 |
1549 |
|
T32 |
93 |
| auto[1] |
5124465 |
1 |
|
|
T30 |
267 |
|
T32 |
51 |
|
T33 |
340 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1474088 |
1 |
|
|
T30 |
73 |
|
T32 |
30 |
|
T33 |
73 |
| auto[1] |
auto[0] |
auto[1] |
1097151 |
1 |
|
|
T30 |
80 |
|
T32 |
12 |
|
T33 |
78 |
| auto[1] |
auto[1] |
auto[0] |
1468767 |
1 |
|
|
T30 |
53 |
|
T32 |
7 |
|
T33 |
85 |
| auto[1] |
auto[1] |
auto[1] |
1084459 |
1 |
|
|
T30 |
61 |
|
T32 |
2 |
|
T33 |
104 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |