Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7209293 |
1 |
|
|
T30 |
226 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5111699 |
1 |
|
|
T30 |
475 |
|
T32 |
46 |
|
T33 |
351 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10134456 |
1 |
|
|
T30 |
462 |
|
T31 |
1549 |
|
T32 |
129 |
| auto[1] |
2186536 |
1 |
|
|
T30 |
239 |
|
T32 |
15 |
|
T33 |
196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7208615 |
1 |
|
|
T30 |
240 |
|
T31 |
1549 |
|
T32 |
90 |
| auto[1] |
5112377 |
1 |
|
|
T30 |
461 |
|
T32 |
54 |
|
T33 |
431 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1471687 |
1 |
|
|
T30 |
98 |
|
T32 |
30 |
|
T33 |
144 |
| auto[1] |
auto[0] |
auto[1] |
1099849 |
1 |
|
|
T30 |
97 |
|
T32 |
7 |
|
T33 |
150 |
| auto[1] |
auto[1] |
auto[0] |
1454154 |
1 |
|
|
T30 |
124 |
|
T32 |
9 |
|
T33 |
91 |
| auto[1] |
auto[1] |
auto[1] |
1086687 |
1 |
|
|
T30 |
142 |
|
T32 |
8 |
|
T33 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |