Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7177269 |
1 |
|
|
T30 |
384 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
5143723 |
1 |
|
|
T30 |
317 |
|
T32 |
33 |
|
T33 |
461 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10156580 |
1 |
|
|
T30 |
478 |
|
T31 |
1549 |
|
T32 |
123 |
| auto[1] |
2164412 |
1 |
|
|
T30 |
223 |
|
T32 |
21 |
|
T33 |
172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7250362 |
1 |
|
|
T30 |
246 |
|
T31 |
1549 |
|
T32 |
117 |
| auto[1] |
5070630 |
1 |
|
|
T30 |
455 |
|
T32 |
27 |
|
T33 |
313 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1442445 |
1 |
|
|
T30 |
133 |
|
T32 |
2 |
|
T33 |
50 |
| auto[1] |
auto[0] |
auto[1] |
1073989 |
1 |
|
|
T30 |
133 |
|
T32 |
21 |
|
T33 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1463773 |
1 |
|
|
T30 |
99 |
|
T32 |
4 |
|
T33 |
91 |
| auto[1] |
auto[1] |
auto[1] |
1090423 |
1 |
|
|
T30 |
90 |
|
T33 |
114 |
|
T35 |
144 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |