Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7206988 |
1 |
|
|
T30 |
297 |
|
T31 |
1549 |
|
T32 |
81 |
| auto[1] |
5114004 |
1 |
|
|
T30 |
404 |
|
T32 |
63 |
|
T33 |
469 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2232319 |
1 |
|
|
T30 |
118 |
|
T32 |
49 |
|
T33 |
147 |
| auto[1] |
auto[0] |
auto[1] |
329027 |
1 |
|
|
T30 |
31 |
|
T32 |
1 |
|
T33 |
39 |
| auto[1] |
auto[1] |
auto[0] |
2223735 |
1 |
|
|
T30 |
200 |
|
T32 |
13 |
|
T33 |
229 |
| auto[1] |
auto[1] |
auto[1] |
328923 |
1 |
|
|
T30 |
55 |
|
T33 |
54 |
|
T35 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |