Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196044 |
1 |
|
|
T30 |
365 |
|
T31 |
1549 |
|
T32 |
92 |
| auto[1] |
5124948 |
1 |
|
|
T30 |
336 |
|
T32 |
52 |
|
T33 |
292 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10131417 |
1 |
|
|
T30 |
476 |
|
T31 |
1549 |
|
T32 |
141 |
| auto[1] |
2189575 |
1 |
|
|
T30 |
225 |
|
T32 |
3 |
|
T33 |
284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7191074 |
1 |
|
|
T30 |
222 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5129918 |
1 |
|
|
T30 |
479 |
|
T32 |
46 |
|
T33 |
584 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1471883 |
1 |
|
|
T30 |
135 |
|
T32 |
28 |
|
T33 |
205 |
| auto[1] |
auto[0] |
auto[1] |
1093748 |
1 |
|
|
T30 |
118 |
|
T33 |
188 |
|
T35 |
214 |
| auto[1] |
auto[1] |
auto[0] |
1468460 |
1 |
|
|
T30 |
119 |
|
T32 |
15 |
|
T33 |
95 |
| auto[1] |
auto[1] |
auto[1] |
1095827 |
1 |
|
|
T30 |
107 |
|
T32 |
3 |
|
T33 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |