Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7195735 |
1 |
|
|
T30 |
179 |
|
T31 |
1549 |
|
T32 |
87 |
| auto[1] |
5125257 |
1 |
|
|
T30 |
522 |
|
T32 |
57 |
|
T33 |
490 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10141057 |
1 |
|
|
T30 |
442 |
|
T31 |
1549 |
|
T32 |
121 |
| auto[1] |
2179935 |
1 |
|
|
T30 |
259 |
|
T32 |
23 |
|
T33 |
297 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204890 |
1 |
|
|
T30 |
183 |
|
T31 |
1549 |
|
T32 |
117 |
| auto[1] |
5116102 |
1 |
|
|
T30 |
518 |
|
T32 |
27 |
|
T33 |
569 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1481328 |
1 |
|
|
T30 |
67 |
|
T32 |
4 |
|
T33 |
114 |
| auto[1] |
auto[0] |
auto[1] |
1094476 |
1 |
|
|
T30 |
53 |
|
T32 |
6 |
|
T33 |
76 |
| auto[1] |
auto[1] |
auto[0] |
1454839 |
1 |
|
|
T30 |
192 |
|
T33 |
158 |
|
T35 |
51 |
| auto[1] |
auto[1] |
auto[1] |
1085459 |
1 |
|
|
T30 |
206 |
|
T32 |
17 |
|
T33 |
221 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |