Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7199085 |
1 |
|
|
T30 |
330 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5121907 |
1 |
|
|
T30 |
371 |
|
T32 |
38 |
|
T33 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10146368 |
1 |
|
|
T30 |
539 |
|
T31 |
1549 |
|
T32 |
134 |
| auto[1] |
2174624 |
1 |
|
|
T30 |
162 |
|
T32 |
10 |
|
T33 |
248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7222187 |
1 |
|
|
T30 |
363 |
|
T31 |
1549 |
|
T32 |
107 |
| auto[1] |
5098805 |
1 |
|
|
T30 |
338 |
|
T32 |
37 |
|
T33 |
475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1467231 |
1 |
|
|
T30 |
77 |
|
T32 |
21 |
|
T33 |
132 |
| auto[1] |
auto[0] |
auto[1] |
1086024 |
1 |
|
|
T30 |
68 |
|
T32 |
3 |
|
T33 |
122 |
| auto[1] |
auto[1] |
auto[0] |
1456950 |
1 |
|
|
T30 |
99 |
|
T32 |
6 |
|
T33 |
95 |
| auto[1] |
auto[1] |
auto[1] |
1088600 |
1 |
|
|
T30 |
94 |
|
T32 |
7 |
|
T33 |
126 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |