Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7189149 |
1 |
|
|
T30 |
338 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5131843 |
1 |
|
|
T30 |
363 |
|
T32 |
38 |
|
T33 |
314 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10121634 |
1 |
|
|
T30 |
519 |
|
T31 |
1549 |
|
T32 |
138 |
| auto[1] |
2199358 |
1 |
|
|
T30 |
182 |
|
T32 |
6 |
|
T33 |
216 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7162388 |
1 |
|
|
T30 |
338 |
|
T31 |
1549 |
|
T32 |
115 |
| auto[1] |
5158604 |
1 |
|
|
T30 |
363 |
|
T32 |
29 |
|
T33 |
391 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1486824 |
1 |
|
|
T30 |
85 |
|
T32 |
13 |
|
T33 |
116 |
| auto[1] |
auto[0] |
auto[1] |
1103190 |
1 |
|
|
T30 |
73 |
|
T32 |
6 |
|
T33 |
144 |
| auto[1] |
auto[1] |
auto[0] |
1472422 |
1 |
|
|
T30 |
96 |
|
T32 |
10 |
|
T33 |
59 |
| auto[1] |
auto[1] |
auto[1] |
1096168 |
1 |
|
|
T30 |
109 |
|
T33 |
72 |
|
T35 |
233 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |