Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7186173 |
1 |
|
|
T30 |
263 |
|
T31 |
1549 |
|
T32 |
117 |
| auto[1] |
5134819 |
1 |
|
|
T30 |
438 |
|
T32 |
27 |
|
T33 |
359 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137962 |
1 |
|
|
T30 |
558 |
|
T31 |
1549 |
|
T32 |
104 |
| auto[1] |
2183030 |
1 |
|
|
T30 |
143 |
|
T32 |
40 |
|
T33 |
143 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196380 |
1 |
|
|
T30 |
441 |
|
T31 |
1549 |
|
T32 |
88 |
| auto[1] |
5124612 |
1 |
|
|
T30 |
260 |
|
T32 |
56 |
|
T33 |
349 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1468977 |
1 |
|
|
T30 |
52 |
|
T32 |
14 |
|
T33 |
109 |
| auto[1] |
auto[0] |
auto[1] |
1089137 |
1 |
|
|
T30 |
78 |
|
T32 |
27 |
|
T33 |
77 |
| auto[1] |
auto[1] |
auto[0] |
1472605 |
1 |
|
|
T30 |
65 |
|
T32 |
2 |
|
T33 |
97 |
| auto[1] |
auto[1] |
auto[1] |
1093893 |
1 |
|
|
T30 |
65 |
|
T32 |
13 |
|
T33 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |