Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7176569 |
1 |
|
|
T30 |
244 |
|
T31 |
1549 |
|
T32 |
93 |
| auto[1] |
5144423 |
1 |
|
|
T30 |
457 |
|
T32 |
51 |
|
T33 |
391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10123841 |
1 |
|
|
T30 |
465 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
2197151 |
1 |
|
|
T30 |
236 |
|
T32 |
33 |
|
T33 |
221 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7172783 |
1 |
|
|
T30 |
241 |
|
T31 |
1549 |
|
T32 |
101 |
| auto[1] |
5148209 |
1 |
|
|
T30 |
460 |
|
T32 |
43 |
|
T33 |
481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1475986 |
1 |
|
|
T30 |
72 |
|
T32 |
5 |
|
T33 |
143 |
| auto[1] |
auto[0] |
auto[1] |
1098262 |
1 |
|
|
T30 |
65 |
|
T32 |
20 |
|
T33 |
109 |
| auto[1] |
auto[1] |
auto[0] |
1475072 |
1 |
|
|
T30 |
152 |
|
T32 |
5 |
|
T33 |
117 |
| auto[1] |
auto[1] |
auto[1] |
1098889 |
1 |
|
|
T30 |
171 |
|
T32 |
13 |
|
T33 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |