Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7175014 |
1 |
|
|
T30 |
267 |
|
T31 |
1549 |
|
T32 |
109 |
| auto[1] |
5145978 |
1 |
|
|
T30 |
434 |
|
T32 |
35 |
|
T33 |
530 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10127453 |
1 |
|
|
T30 |
547 |
|
T31 |
1549 |
|
T32 |
108 |
| auto[1] |
2193539 |
1 |
|
|
T30 |
154 |
|
T32 |
36 |
|
T33 |
209 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7183277 |
1 |
|
|
T30 |
387 |
|
T31 |
1549 |
|
T32 |
97 |
| auto[1] |
5137715 |
1 |
|
|
T30 |
314 |
|
T32 |
47 |
|
T33 |
357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1460011 |
1 |
|
|
T30 |
99 |
|
T32 |
10 |
|
T33 |
40 |
| auto[1] |
auto[0] |
auto[1] |
1095803 |
1 |
|
|
T30 |
89 |
|
T32 |
21 |
|
T33 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1484165 |
1 |
|
|
T30 |
61 |
|
T32 |
1 |
|
T33 |
108 |
| auto[1] |
auto[1] |
auto[1] |
1097736 |
1 |
|
|
T30 |
65 |
|
T32 |
15 |
|
T33 |
167 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |