Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7172659 |
1 |
|
|
T30 |
521 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
5148333 |
1 |
|
|
T30 |
180 |
|
T32 |
33 |
|
T33 |
343 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10130161 |
1 |
|
|
T30 |
529 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
2190831 |
1 |
|
|
T30 |
172 |
|
T32 |
33 |
|
T33 |
204 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7177138 |
1 |
|
|
T30 |
338 |
|
T31 |
1549 |
|
T32 |
100 |
| auto[1] |
5143854 |
1 |
|
|
T30 |
363 |
|
T32 |
44 |
|
T33 |
412 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1471949 |
1 |
|
|
T30 |
116 |
|
T32 |
6 |
|
T33 |
124 |
| auto[1] |
auto[0] |
auto[1] |
1094858 |
1 |
|
|
T30 |
100 |
|
T32 |
24 |
|
T33 |
123 |
| auto[1] |
auto[1] |
auto[0] |
1481074 |
1 |
|
|
T30 |
75 |
|
T32 |
5 |
|
T33 |
84 |
| auto[1] |
auto[1] |
auto[1] |
1095973 |
1 |
|
|
T30 |
72 |
|
T32 |
9 |
|
T33 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |