Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7233040 |
1 |
|
|
T30 |
372 |
|
T31 |
1549 |
|
T32 |
82 |
| auto[1] |
5087952 |
1 |
|
|
T30 |
329 |
|
T32 |
62 |
|
T33 |
361 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137648 |
1 |
|
|
T30 |
440 |
|
T31 |
1549 |
|
T32 |
127 |
| auto[1] |
2183344 |
1 |
|
|
T30 |
261 |
|
T32 |
17 |
|
T33 |
222 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7200530 |
1 |
|
|
T30 |
212 |
|
T31 |
1549 |
|
T32 |
110 |
| auto[1] |
5120462 |
1 |
|
|
T30 |
489 |
|
T32 |
34 |
|
T33 |
446 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1479595 |
1 |
|
|
T30 |
91 |
|
T32 |
7 |
|
T33 |
122 |
| auto[1] |
auto[0] |
auto[1] |
1096114 |
1 |
|
|
T30 |
111 |
|
T32 |
3 |
|
T33 |
128 |
| auto[1] |
auto[1] |
auto[0] |
1457523 |
1 |
|
|
T30 |
137 |
|
T32 |
10 |
|
T33 |
102 |
| auto[1] |
auto[1] |
auto[1] |
1087230 |
1 |
|
|
T30 |
150 |
|
T32 |
14 |
|
T33 |
94 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |