Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7211377 |
1 |
|
|
T30 |
306 |
|
T31 |
1549 |
|
T32 |
98 |
| auto[1] |
5109615 |
1 |
|
|
T30 |
395 |
|
T32 |
46 |
|
T33 |
346 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10128660 |
1 |
|
|
T30 |
470 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
2192332 |
1 |
|
|
T30 |
231 |
|
T32 |
38 |
|
T33 |
249 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7183474 |
1 |
|
|
T30 |
222 |
|
T31 |
1549 |
|
T32 |
105 |
| auto[1] |
5137518 |
1 |
|
|
T30 |
479 |
|
T32 |
39 |
|
T33 |
479 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1477593 |
1 |
|
|
T30 |
144 |
|
T33 |
126 |
|
T35 |
30 |
| auto[1] |
auto[0] |
auto[1] |
1102832 |
1 |
|
|
T30 |
137 |
|
T32 |
15 |
|
T33 |
135 |
| auto[1] |
auto[1] |
auto[0] |
1467593 |
1 |
|
|
T30 |
104 |
|
T32 |
1 |
|
T33 |
104 |
| auto[1] |
auto[1] |
auto[1] |
1089500 |
1 |
|
|
T30 |
94 |
|
T32 |
23 |
|
T33 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |