Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7229953 |
1 |
|
|
T30 |
494 |
|
T31 |
1549 |
|
T32 |
111 |
| auto[1] |
5091039 |
1 |
|
|
T30 |
207 |
|
T32 |
33 |
|
T33 |
391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11665722 |
1 |
|
|
T30 |
623 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
655270 |
1 |
|
|
T30 |
78 |
|
T32 |
1 |
|
T33 |
56 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7219718 |
1 |
|
|
T30 |
311 |
|
T31 |
1549 |
|
T32 |
83 |
| auto[1] |
5101274 |
1 |
|
|
T30 |
390 |
|
T32 |
61 |
|
T33 |
360 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2248041 |
1 |
|
|
T30 |
267 |
|
T32 |
42 |
|
T33 |
202 |
| auto[1] |
auto[0] |
auto[1] |
332230 |
1 |
|
|
T30 |
64 |
|
T33 |
38 |
|
T35 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2197963 |
1 |
|
|
T30 |
45 |
|
T32 |
18 |
|
T33 |
102 |
| auto[1] |
auto[1] |
auto[1] |
323040 |
1 |
|
|
T30 |
14 |
|
T32 |
1 |
|
T33 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |