Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7202985 |
1 |
|
|
T30 |
536 |
|
T31 |
1549 |
|
T32 |
89 |
| auto[1] |
5118007 |
1 |
|
|
T30 |
165 |
|
T32 |
55 |
|
T33 |
402 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10145625 |
1 |
|
|
T30 |
554 |
|
T31 |
1549 |
|
T32 |
123 |
| auto[1] |
2175367 |
1 |
|
|
T30 |
147 |
|
T32 |
21 |
|
T33 |
185 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7200424 |
1 |
|
|
T30 |
427 |
|
T31 |
1549 |
|
T32 |
88 |
| auto[1] |
5120568 |
1 |
|
|
T30 |
274 |
|
T32 |
56 |
|
T33 |
357 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1472265 |
1 |
|
|
T30 |
89 |
|
T32 |
27 |
|
T33 |
55 |
| auto[1] |
auto[0] |
auto[1] |
1089140 |
1 |
|
|
T30 |
106 |
|
T32 |
10 |
|
T33 |
70 |
| auto[1] |
auto[1] |
auto[0] |
1472936 |
1 |
|
|
T30 |
38 |
|
T32 |
8 |
|
T33 |
117 |
| auto[1] |
auto[1] |
auto[1] |
1086227 |
1 |
|
|
T30 |
41 |
|
T32 |
11 |
|
T33 |
115 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |