Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198594 |
1 |
|
|
T30 |
194 |
|
T31 |
1549 |
|
T32 |
93 |
| auto[1] |
5122398 |
1 |
|
|
T30 |
507 |
|
T32 |
51 |
|
T33 |
468 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137610 |
1 |
|
|
T30 |
465 |
|
T31 |
1549 |
|
T32 |
101 |
| auto[1] |
2183382 |
1 |
|
|
T30 |
236 |
|
T32 |
43 |
|
T33 |
223 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7189969 |
1 |
|
|
T30 |
202 |
|
T31 |
1549 |
|
T32 |
94 |
| auto[1] |
5131023 |
1 |
|
|
T30 |
499 |
|
T32 |
50 |
|
T33 |
450 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1469588 |
1 |
|
|
T30 |
100 |
|
T32 |
2 |
|
T33 |
73 |
| auto[1] |
auto[0] |
auto[1] |
1089151 |
1 |
|
|
T30 |
75 |
|
T32 |
30 |
|
T33 |
88 |
| auto[1] |
auto[1] |
auto[0] |
1478053 |
1 |
|
|
T30 |
163 |
|
T32 |
5 |
|
T33 |
154 |
| auto[1] |
auto[1] |
auto[1] |
1094231 |
1 |
|
|
T30 |
161 |
|
T32 |
13 |
|
T33 |
135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |