Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7187922 |
1 |
|
|
T30 |
281 |
|
T31 |
1549 |
|
T32 |
91 |
| auto[1] |
5133070 |
1 |
|
|
T30 |
420 |
|
T32 |
53 |
|
T33 |
647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10137844 |
1 |
|
|
T30 |
526 |
|
T31 |
1549 |
|
T32 |
125 |
| auto[1] |
2183148 |
1 |
|
|
T30 |
175 |
|
T32 |
19 |
|
T33 |
198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7194135 |
1 |
|
|
T30 |
339 |
|
T31 |
1549 |
|
T32 |
112 |
| auto[1] |
5126857 |
1 |
|
|
T30 |
362 |
|
T32 |
32 |
|
T33 |
399 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1464805 |
1 |
|
|
T30 |
90 |
|
T32 |
1 |
|
T33 |
53 |
| auto[1] |
auto[0] |
auto[1] |
1092633 |
1 |
|
|
T30 |
89 |
|
T32 |
14 |
|
T33 |
42 |
| auto[1] |
auto[1] |
auto[0] |
1478904 |
1 |
|
|
T30 |
97 |
|
T32 |
12 |
|
T33 |
148 |
| auto[1] |
auto[1] |
auto[1] |
1090515 |
1 |
|
|
T30 |
86 |
|
T32 |
5 |
|
T33 |
156 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |