Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7216970 |
1 |
|
|
T30 |
202 |
|
T31 |
1549 |
|
T32 |
99 |
| auto[1] |
5104022 |
1 |
|
|
T30 |
499 |
|
T32 |
45 |
|
T33 |
254 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661944 |
1 |
|
|
T30 |
650 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
659048 |
1 |
|
|
T30 |
51 |
|
T33 |
84 |
|
T35 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7187684 |
1 |
|
|
T30 |
479 |
|
T31 |
1549 |
|
T32 |
90 |
| auto[1] |
5133308 |
1 |
|
|
T30 |
222 |
|
T32 |
54 |
|
T33 |
466 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2256649 |
1 |
|
|
T30 |
110 |
|
T32 |
32 |
|
T33 |
238 |
| auto[1] |
auto[0] |
auto[1] |
332900 |
1 |
|
|
T30 |
30 |
|
T33 |
52 |
|
T35 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2217611 |
1 |
|
|
T30 |
61 |
|
T32 |
22 |
|
T33 |
144 |
| auto[1] |
auto[1] |
auto[1] |
326148 |
1 |
|
|
T30 |
21 |
|
T33 |
32 |
|
T35 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |