Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7186279 |
1 |
|
|
T30 |
350 |
|
T31 |
1549 |
|
T32 |
106 |
| auto[1] |
5134713 |
1 |
|
|
T30 |
351 |
|
T32 |
38 |
|
T33 |
442 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661388 |
1 |
|
|
T30 |
634 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
659604 |
1 |
|
|
T30 |
67 |
|
T33 |
79 |
|
T35 |
35 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7181979 |
1 |
|
|
T30 |
322 |
|
T31 |
1549 |
|
T32 |
105 |
| auto[1] |
5139013 |
1 |
|
|
T30 |
379 |
|
T32 |
39 |
|
T33 |
452 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2233571 |
1 |
|
|
T30 |
156 |
|
T32 |
32 |
|
T33 |
210 |
| auto[1] |
auto[0] |
auto[1] |
327741 |
1 |
|
|
T30 |
30 |
|
T33 |
43 |
|
T35 |
18 |
| auto[1] |
auto[1] |
auto[0] |
2245838 |
1 |
|
|
T30 |
156 |
|
T32 |
7 |
|
T33 |
163 |
| auto[1] |
auto[1] |
auto[1] |
331863 |
1 |
|
|
T30 |
37 |
|
T33 |
36 |
|
T35 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |