Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7181704 |
1 |
|
|
T30 |
426 |
|
T31 |
1549 |
|
T32 |
107 |
| auto[1] |
5139288 |
1 |
|
|
T30 |
275 |
|
T32 |
37 |
|
T33 |
352 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11661106 |
1 |
|
|
T30 |
634 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
659886 |
1 |
|
|
T30 |
67 |
|
T32 |
1 |
|
T33 |
86 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196396 |
1 |
|
|
T30 |
369 |
|
T31 |
1549 |
|
T32 |
95 |
| auto[1] |
5124596 |
1 |
|
|
T30 |
332 |
|
T32 |
49 |
|
T33 |
443 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2249328 |
1 |
|
|
T30 |
114 |
|
T32 |
34 |
|
T33 |
193 |
| auto[1] |
auto[0] |
auto[1] |
333029 |
1 |
|
|
T30 |
34 |
|
T32 |
1 |
|
T33 |
45 |
| auto[1] |
auto[1] |
auto[0] |
2215382 |
1 |
|
|
T30 |
151 |
|
T32 |
14 |
|
T33 |
164 |
| auto[1] |
auto[1] |
auto[1] |
326857 |
1 |
|
|
T30 |
33 |
|
T33 |
41 |
|
T35 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |