Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7185759 |
1 |
|
|
T30 |
416 |
|
T31 |
1549 |
|
T32 |
95 |
| auto[1] |
5135233 |
1 |
|
|
T30 |
285 |
|
T32 |
49 |
|
T33 |
544 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662623 |
1 |
|
|
T30 |
640 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
658369 |
1 |
|
|
T30 |
61 |
|
T33 |
71 |
|
T35 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7198589 |
1 |
|
|
T30 |
405 |
|
T31 |
1549 |
|
T32 |
124 |
| auto[1] |
5122403 |
1 |
|
|
T30 |
296 |
|
T32 |
20 |
|
T33 |
342 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2240074 |
1 |
|
|
T30 |
150 |
|
T32 |
2 |
|
T33 |
123 |
| auto[1] |
auto[0] |
auto[1] |
329818 |
1 |
|
|
T30 |
42 |
|
T33 |
33 |
|
T35 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2223960 |
1 |
|
|
T30 |
85 |
|
T32 |
18 |
|
T33 |
148 |
| auto[1] |
auto[1] |
auto[1] |
328551 |
1 |
|
|
T30 |
19 |
|
T33 |
38 |
|
T35 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |