Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7204034 |
1 |
|
|
T30 |
549 |
|
T31 |
1549 |
|
T32 |
102 |
| auto[1] |
5116958 |
1 |
|
|
T30 |
152 |
|
T32 |
42 |
|
T33 |
254 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11663649 |
1 |
|
|
T30 |
626 |
|
T31 |
1549 |
|
T32 |
143 |
| auto[1] |
657343 |
1 |
|
|
T30 |
75 |
|
T32 |
1 |
|
T33 |
78 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7212037 |
1 |
|
|
T30 |
344 |
|
T31 |
1549 |
|
T32 |
97 |
| auto[1] |
5108955 |
1 |
|
|
T30 |
357 |
|
T32 |
47 |
|
T33 |
421 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2234948 |
1 |
|
|
T30 |
205 |
|
T32 |
36 |
|
T33 |
274 |
| auto[1] |
auto[0] |
auto[1] |
331007 |
1 |
|
|
T30 |
52 |
|
T32 |
1 |
|
T33 |
60 |
| auto[1] |
auto[1] |
auto[0] |
2216664 |
1 |
|
|
T30 |
77 |
|
T32 |
10 |
|
T33 |
69 |
| auto[1] |
auto[1] |
auto[1] |
326336 |
1 |
|
|
T30 |
23 |
|
T33 |
18 |
|
T35 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |