Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7214324 |
1 |
|
|
T30 |
449 |
|
T31 |
1549 |
|
T32 |
103 |
| auto[1] |
5106668 |
1 |
|
|
T30 |
252 |
|
T32 |
41 |
|
T33 |
348 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11662635 |
1 |
|
|
T30 |
618 |
|
T31 |
1549 |
|
T32 |
144 |
| auto[1] |
658357 |
1 |
|
|
T30 |
83 |
|
T33 |
87 |
|
T35 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7196094 |
1 |
|
|
T30 |
266 |
|
T31 |
1549 |
|
T32 |
108 |
| auto[1] |
5124898 |
1 |
|
|
T30 |
435 |
|
T32 |
36 |
|
T33 |
436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2243913 |
1 |
|
|
T30 |
241 |
|
T32 |
19 |
|
T33 |
212 |
| auto[1] |
auto[0] |
auto[1] |
331385 |
1 |
|
|
T30 |
58 |
|
T33 |
59 |
|
T35 |
11 |
| auto[1] |
auto[1] |
auto[0] |
2222628 |
1 |
|
|
T30 |
111 |
|
T32 |
17 |
|
T33 |
137 |
| auto[1] |
auto[1] |
auto[1] |
326972 |
1 |
|
|
T30 |
25 |
|
T33 |
28 |
|
T35 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |