Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3769877	1			T23	1		T24	851		T25	21360
all_pins[1]	3769877	1			T23	1		T24	851		T25	21360
all_pins[2]	3769877	1			T23	1		T24	851		T25	21360
all_pins[3]	3769877	1			T23	1		T24	851		T25	21360
all_pins[4]	3769877	1			T23	1		T24	851		T25	21360
all_pins[5]	3769877	1			T23	1		T24	851		T25	21360
all_pins[6]	3769877	1			T23	1		T24	851		T25	21360
all_pins[7]	3769877	1			T23	1		T24	851		T25	21360
all_pins[8]	3769877	1			T23	1		T24	851		T25	21360
all_pins[9]	3769877	1			T23	1		T24	851		T25	21360
all_pins[10]	3769877	1			T23	1		T24	851		T25	21360
all_pins[11]	3769877	1			T23	1		T24	851		T25	21360
all_pins[12]	3769877	1			T23	1		T24	851		T25	21360
all_pins[13]	3769877	1			T23	1		T24	851		T25	21360
all_pins[14]	3769877	1			T23	1		T24	851		T25	21360
all_pins[15]	3769877	1			T23	1		T24	851		T25	21360
all_pins[16]	3769877	1			T23	1		T24	851		T25	21360
all_pins[17]	3769877	1			T23	1		T24	851		T25	21360
all_pins[18]	3769877	1			T23	1		T24	851		T25	21360
all_pins[19]	3769877	1			T23	1		T24	851		T25	21360
all_pins[20]	3769877	1			T23	1		T24	851		T25	21360
all_pins[21]	3769877	1			T23	1		T24	851		T25	21360
all_pins[22]	3769877	1			T23	1		T24	851		T25	21360
all_pins[23]	3769877	1			T23	1		T24	851		T25	21360
all_pins[24]	3769877	1			T23	1		T24	851		T25	21360
all_pins[25]	3769877	1			T23	1		T24	851		T25	21360
all_pins[26]	3769877	1			T23	1		T24	851		T25	21360
all_pins[27]	3769877	1			T23	1		T24	851		T25	21360
all_pins[28]	3769877	1			T23	1		T24	851		T25	21360
all_pins[29]	3769877	1			T23	1		T24	851		T25	21360
all_pins[30]	3769877	1			T23	1		T24	851		T25	21360
all_pins[31]	3769877	1			T23	1		T24	851		T25	21360

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	74944822	1			T23	32		T24	16856		T25	420559
values[0x1]	45691242	1			T24	10376		T25	262961		T28	8202
transitions[0x0=>0x1]	27380831	1			T24	6151		T25	156055		T28	4760
transitions[0x1=>0x0]	27380659	1			T24	6151		T25	156055		T28	4760

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2340587	1			T23	1		T24	432		T25	13023
all_pins[0]	values[0x1]	1429290	1			T24	419		T25	8337		T28	186
all_pins[0]	transitions[0x0=>0x1]	883587	1			T24	300		T25	4959		T28	116
all_pins[0]	transitions[0x1=>0x0]	883287	1			T24	193		T25	4803		T28	178
all_pins[1]	values[0x0]	2343805	1			T23	1		T24	504		T25	12989
all_pins[1]	values[0x1]	1426072	1			T24	347		T25	8371		T28	203
all_pins[1]	transitions[0x0=>0x1]	851651	1			T24	152		T25	4873		T28	142
all_pins[1]	transitions[0x1=>0x0]	854869	1			T24	224		T25	4839		T28	125
all_pins[2]	values[0x0]	2343216	1			T23	1		T24	483		T25	13248
all_pins[2]	values[0x1]	1426661	1			T24	368		T25	8112		T28	254
all_pins[2]	transitions[0x0=>0x1]	853629	1			T24	203		T25	4714		T28	178
all_pins[2]	transitions[0x1=>0x0]	853040	1			T24	182		T25	4973		T28	127
all_pins[3]	values[0x0]	2340537	1			T23	1		T24	576		T25	13228
all_pins[3]	values[0x1]	1429340	1			T24	275		T25	8132		T28	247
all_pins[3]	transitions[0x0=>0x1]	857128	1			T24	173		T25	4841		T28	125
all_pins[3]	transitions[0x1=>0x0]	854449	1			T24	266		T25	4821		T28	132
all_pins[4]	values[0x0]	2343711	1			T23	1		T24	559		T25	13019
all_pins[4]	values[0x1]	1426166	1			T24	292		T25	8341		T28	243
all_pins[4]	transitions[0x0=>0x1]	853334	1			T24	175		T25	5006		T28	135
all_pins[4]	transitions[0x1=>0x0]	856508	1			T24	158		T25	4797		T28	139
all_pins[5]	values[0x0]	2334796	1			T23	1		T24	479		T25	12862
all_pins[5]	values[0x1]	1435081	1			T24	372		T25	8498		T28	251
all_pins[5]	transitions[0x0=>0x1]	857838	1			T24	234		T25	5082		T28	148
all_pins[5]	transitions[0x1=>0x0]	848923	1			T24	154		T25	4925		T28	140
all_pins[6]	values[0x0]	2340199	1			T23	1		T24	524		T25	13315
all_pins[6]	values[0x1]	1429678	1			T24	327		T25	8045		T28	289
all_pins[6]	transitions[0x0=>0x1]	854984	1			T24	130		T25	4719		T28	172
all_pins[6]	transitions[0x1=>0x0]	860387	1			T24	175		T25	5172		T28	134
all_pins[7]	values[0x0]	2342183	1			T23	1		T24	460		T25	13041
all_pins[7]	values[0x1]	1427694	1			T24	391		T25	8319		T28	233
all_pins[7]	transitions[0x0=>0x1]	855720	1			T24	188		T25	4877		T28	117
all_pins[7]	transitions[0x1=>0x0]	857704	1			T24	124		T25	4603		T28	173
all_pins[8]	values[0x0]	2341679	1			T23	1		T24	552		T25	13136
all_pins[8]	values[0x1]	1428198	1			T24	299		T25	8224		T28	263
all_pins[8]	transitions[0x0=>0x1]	855007	1			T24	158		T25	4924		T28	161
all_pins[8]	transitions[0x1=>0x0]	854503	1			T24	250		T25	5019		T28	131
all_pins[9]	values[0x0]	2346415	1			T23	1		T24	645		T25	12993
all_pins[9]	values[0x1]	1423462	1			T24	206		T25	8367		T28	261
all_pins[9]	transitions[0x0=>0x1]	848911	1			T24	93		T25	5005		T28	151
all_pins[9]	transitions[0x1=>0x0]	853647	1			T24	186		T25	4862		T28	153
all_pins[10]	values[0x0]	2348140	1			T23	1		T24	521		T25	12984
all_pins[10]	values[0x1]	1421737	1			T24	330		T25	8376		T28	294
all_pins[10]	transitions[0x0=>0x1]	852424	1			T24	276		T25	4853		T28	198
all_pins[10]	transitions[0x1=>0x0]	854149	1			T24	152		T25	4844		T28	165
all_pins[11]	values[0x0]	2340407	1			T23	1		T24	705		T25	13214
all_pins[11]	values[0x1]	1429470	1			T24	146		T25	8146		T28	270
all_pins[11]	transitions[0x0=>0x1]	859129	1			T24	108		T25	4745		T28	144
all_pins[11]	transitions[0x1=>0x0]	851396	1			T24	292		T25	4975		T28	168
all_pins[12]	values[0x0]	2338234	1			T23	1		T24	441		T25	13049
all_pins[12]	values[0x1]	1431643	1			T24	410		T25	8311		T28	275
all_pins[12]	transitions[0x0=>0x1]	855875	1			T24	356		T25	4889		T28	136
all_pins[12]	transitions[0x1=>0x0]	853702	1			T24	92		T25	4724		T28	131
all_pins[13]	values[0x0]	2338369	1			T23	1		T24	474		T25	13509
all_pins[13]	values[0x1]	1431508	1			T24	377		T25	7851		T28	266
all_pins[13]	transitions[0x0=>0x1]	854798	1			T24	140		T25	4618		T28	154
all_pins[13]	transitions[0x1=>0x0]	854933	1			T24	173		T25	5078		T28	163
all_pins[14]	values[0x0]	2344289	1			T23	1		T24	479		T25	13167
all_pins[14]	values[0x1]	1425588	1			T24	372		T25	8193		T28	231
all_pins[14]	transitions[0x0=>0x1]	851021	1			T24	174		T25	4850		T28	153
all_pins[14]	transitions[0x1=>0x0]	856941	1			T24	179		T25	4508		T28	188
all_pins[15]	values[0x0]	2342192	1			T23	1		T24	602		T25	13433
all_pins[15]	values[0x1]	1427685	1			T24	249		T25	7927		T28	197
all_pins[15]	transitions[0x0=>0x1]	855767	1			T24	109		T25	5004		T28	121
all_pins[15]	transitions[0x1=>0x0]	853670	1			T24	232		T25	5270		T28	155
all_pins[16]	values[0x0]	2345338	1			T23	1		T24	445		T25	13133
all_pins[16]	values[0x1]	1424539	1			T24	406		T25	8227		T28	292
all_pins[16]	transitions[0x0=>0x1]	853759	1			T24	314		T25	5030		T28	210
all_pins[16]	transitions[0x1=>0x0]	856905	1			T24	157		T25	4730		T28	115
all_pins[17]	values[0x0]	2344412	1			T23	1		T24	466		T25	13112
all_pins[17]	values[0x1]	1425465	1			T24	385		T25	8248		T28	269
all_pins[17]	transitions[0x0=>0x1]	856019	1			T24	158		T25	4858		T28	127
all_pins[17]	transitions[0x1=>0x0]	855093	1			T24	179		T25	4837		T28	150
all_pins[18]	values[0x0]	2344078	1			T23	1		T24	489		T25	13245
all_pins[18]	values[0x1]	1425799	1			T24	362		T25	8115		T28	268
all_pins[18]	transitions[0x0=>0x1]	856102	1			T24	213		T25	4820		T28	144
all_pins[18]	transitions[0x1=>0x0]	855768	1			T24	236		T25	4953		T28	145
all_pins[19]	values[0x0]	2339923	1			T23	1		T24	588		T25	13002
all_pins[19]	values[0x1]	1429954	1			T24	263		T25	8358		T28	254
all_pins[19]	transitions[0x0=>0x1]	855787	1			T24	143		T25	5000		T28	127
all_pins[19]	transitions[0x1=>0x0]	851632	1			T24	242		T25	4757		T28	141
all_pins[20]	values[0x0]	2337843	1			T23	1		T24	511		T25	13098
all_pins[20]	values[0x1]	1432034	1			T24	340		T25	8262		T28	259
all_pins[20]	transitions[0x0=>0x1]	857460	1			T24	268		T25	4946		T28	143
all_pins[20]	transitions[0x1=>0x0]	855380	1			T24	191		T25	5042		T28	138
all_pins[21]	values[0x0]	2342242	1			T23	1		T24	642		T25	13119
all_pins[21]	values[0x1]	1427635	1			T24	209		T25	8241		T28	270
all_pins[21]	transitions[0x0=>0x1]	852236	1			T24	141		T25	4658		T28	153
all_pins[21]	transitions[0x1=>0x0]	856635	1			T24	272		T25	4679		T28	142
all_pins[22]	values[0x0]	2346633	1			T23	1		T24	569		T25	12865
all_pins[22]	values[0x1]	1423244	1			T24	282		T25	8495		T28	226
all_pins[22]	transitions[0x0=>0x1]	851217	1			T24	199		T25	5079		T28	139
all_pins[22]	transitions[0x1=>0x0]	855608	1			T24	126		T25	4825		T28	183
all_pins[23]	values[0x0]	2344564	1			T23	1		T24	420		T25	13311
all_pins[23]	values[0x1]	1425313	1			T24	431		T25	8049		T28	245
all_pins[23]	transitions[0x0=>0x1]	855711	1			T24	277		T25	4677		T28	167
all_pins[23]	transitions[0x1=>0x0]	853642	1			T24	128		T25	5123		T28	148
all_pins[24]	values[0x0]	2339631	1			T23	1		T24	570		T25	13242
all_pins[24]	values[0x1]	1430246	1			T24	281		T25	8118		T28	239
all_pins[24]	transitions[0x0=>0x1]	857764	1			T24	131		T25	5028		T28	167
all_pins[24]	transitions[0x1=>0x0]	852831	1			T24	281		T25	4959		T28	173
all_pins[25]	values[0x0]	2343463	1			T23	1		T24	458		T25	13376
all_pins[25]	values[0x1]	1426414	1			T24	393		T25	7984		T28	292
all_pins[25]	transitions[0x0=>0x1]	854394	1			T24	259		T25	4847		T28	172
all_pins[25]	transitions[0x1=>0x0]	858226	1			T24	147		T25	4981		T28	119
all_pins[26]	values[0x0]	2333733	1			T23	1		T24	500		T25	13031
all_pins[26]	values[0x1]	1436144	1			T24	351		T25	8329		T28	258
all_pins[26]	transitions[0x0=>0x1]	860239	1			T24	207		T25	5110		T28	140
all_pins[26]	transitions[0x1=>0x0]	850509	1			T24	249		T25	4765		T28	174
all_pins[27]	values[0x0]	2342737	1			T23	1		T24	567		T25	12989
all_pins[27]	values[0x1]	1427140	1			T24	284		T25	8371		T28	275
all_pins[27]	transitions[0x0=>0x1]	850223	1			T24	152		T25	4975		T28	157
all_pins[27]	transitions[0x1=>0x0]	859227	1			T24	219		T25	4933		T28	140
all_pins[28]	values[0x0]	2342290	1			T23	1		T24	502		T25	13223
all_pins[28]	values[0x1]	1427587	1			T24	349		T25	8137		T28	308
all_pins[28]	transitions[0x0=>0x1]	853772	1			T24	171		T25	4833		T28	151
all_pins[28]	transitions[0x1=>0x0]	853325	1			T24	106		T25	5067		T28	118
all_pins[29]	values[0x0]	2347510	1			T23	1		T24	553		T25	13296
all_pins[29]	values[0x1]	1422367	1			T24	298		T25	8064		T28	270
all_pins[29]	transitions[0x0=>0x1]	852754	1			T24	170		T25	4589		T28	137
all_pins[29]	transitions[0x1=>0x0]	857974	1			T24	221		T25	4662		T28	175
all_pins[30]	values[0x0]	2340951	1			T23	1		T24	601		T25	13128
all_pins[30]	values[0x1]	1428926	1			T24	250		T25	8232		T28	266
all_pins[30]	transitions[0x0=>0x1]	857079	1			T24	157		T25	4848		T28	126
all_pins[30]	transitions[0x1=>0x0]	850520	1			T24	205		T25	4680		T28	130
all_pins[31]	values[0x0]	2340715	1			T23	1		T24	539		T25	13179
all_pins[31]	values[0x1]	1429162	1			T24	312		T25	8181		T28	248
all_pins[31]	transitions[0x0=>0x1]	855512	1			T24	222		T25	4798		T28	149
all_pins[31]	transitions[0x1=>0x0]	855276	1			T24	160		T25	4849		T28	167