Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[1]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[2]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[3]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[4]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[5]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[6]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[7]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[8]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[9]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[10]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[11]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[12]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[13]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[14]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[15]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[16]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[17]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[18]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[19]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[20]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[21]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[22]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[23]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[24]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[25]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[26]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[27]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[28]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[29]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[30]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[31]	12568570	1			T23	1		T24	1546		T25	62868

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239790046

1

T23

32

T24

24557

T25

130645

auto[1]

162404194

1

T24

24915

T25

705321

T26

14839

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323951071

1

T23

32

T24

49472

T25

160285

auto[1]

78243169

1

T25

408921

T26

8142

T27

3674

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301013166

1

T23

32

T24

49472

T25

146477

auto[1]

101181074

1

T25

547006

T26

8474

T27

7403

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4704995	1			T23	1		T24	726		T25	24349
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3473140	1			T24	820		T25	14805		T26	211
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1232326	1			T25	6403		T26	132		T27	50
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1557425	1			T25	10428		T27	149		T28	15
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	379504	1			T25	830		T26	106		T27	19
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1221180	1			T25	6053		T26	133		T27	55
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4700022	1			T23	1		T24	781		T25	24509
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3471779	1			T24	765		T25	15044		T26	170
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1229611	1			T25	6331		T26	120		T27	58
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1562016	1			T25	10142		T27	128		T28	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	381715	1			T25	818		T26	135		T27	15
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1223427	1			T25	6024		T26	152		T27	63
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4704528	1			T23	1		T24	758		T25	24451
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3474192	1			T24	788		T25	15033		T26	178
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1230595	1			T25	6488		T26	141		T27	41
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1564731	1			T25	9845		T27	162		T28	19
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	377150	1			T25	793		T26	128		T27	23
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1217374	1			T25	6258		T26	128		T27	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4694608	1			T23	1		T24	752		T25	24899
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3482494	1			T24	794		T25	15127		T26	187
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1230003	1			T25	6465		T26	92		T27	66
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1559888	1			T25	9681		T27	114		T28	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	377977	1			T25	775		T26	172		T27	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1223600	1			T25	5921		T26	144		T27	37
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4694027	1			T23	1		T24	768		T25	24253
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3478267	1			T24	778		T25	14853		T26	187
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1227496	1			T25	6312		T26	122		T27	25
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1566518	1			T25	9904		T27	166		T28	18
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	379462	1			T25	801		T26	138		T27	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1222800	1			T25	6745		T26	150		T27	49
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4690894	1			T23	1		T24	778		T25	24084
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3487279	1			T24	768		T25	14958		T26	187
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1231066	1			T25	7029		T26	135		T27	51
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1564020	1			T25	9814		T27	109		T28	14
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	378630	1			T25	780		T26	122		T27	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1216681	1			T25	6203		T26	150		T27	70
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4711214	1			T23	1		T24	764		T25	24612
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3475078	1			T24	782		T25	14699		T26	195
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1231660	1			T25	6450		T26	131		T27	52
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1556225	1			T25	10192		T27	215		T28	13
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	378425	1			T25	846		T26	126		T27	36
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1215968	1			T25	6069		T26	134		T27	55
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4697483	1			T23	1		T24	784		T25	24371
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3479877	1			T24	762		T25	15028		T26	198
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1226940	1			T25	6392		T26	132		T27	69
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1566393	1			T25	9979		T27	132		T28	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	379361	1			T25	791		T26	118		T27	27
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1218516	1			T25	6307		T26	145		T27	48
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4696483	1			T23	1		T24	802		T25	24043
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3480165	1			T24	744		T25	15055		T26	197
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1229931	1			T25	6556		T26	125		T27	61
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1563796	1			T25	10045		T27	133		T28	11
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	380066	1			T25	690		T26	124		T27	22
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1218129	1			T25	6479		T26	144		T27	70
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4698145	1			T23	1		T24	769		T25	24527
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3476936	1			T24	777		T25	14903		T26	185
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1234739	1			T25	6307		T26	146		T27	52
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1560461	1			T25	10001		T27	167		T28	17
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	378986	1			T25	838		T26	129		T27	40
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1219303	1			T25	6292		T26	130		T27	77
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4687269	1			T23	1		T24	787		T25	24090
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3483500	1			T24	759		T25	14889		T26	186
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1227848	1			T25	6510		T26	129		T27	22
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1566812	1			T25	10005		T27	176		T28	6
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	382220	1			T25	816		T26	148		T27	33
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1220921	1			T25	6558		T26	120		T27	90
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4693925	1			T23	1		T24	727		T25	24558
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3482973	1			T24	819		T25	14954		T26	230
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1231295	1			T25	6840		T26	134		T27	67
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1560455	1			T25	9540		T27	150		T28	14
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	381184	1			T25	784		T26	137		T27	23
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1218738	1			T25	6192		T26	94		T27	84
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4683865	1			T23	1		T24	737		T25	24269
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3487594	1			T24	809		T25	14860		T26	213
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1233072	1			T25	6478		T26	108		T27	49
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1566219	1			T25	9820		T27	186		T28	17
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	377910	1			T25	831		T26	156		T27	30
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1219910	1			T25	6610		T26	120		T27	94
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4708834	1			T23	1		T24	776		T25	24473
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3467345	1			T24	770		T25	14877		T26	221
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1231870	1			T25	6188		T26	116		T27	37
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1558502	1			T25	10272		T27	208		T28	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	378142	1			T25	831		T26	120		T27	28
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1223877	1			T25	6227		T26	136		T27	43
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4704006	1			T23	1		T24	776		T25	24618
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3473954	1			T24	770		T25	14909		T26	178
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1227920	1			T25	6458		T26	110		T27	73
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1566840	1			T25	10110		T27	150		T28	12
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	377891	1			T25	743		T26	161		T27	21
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1217959	1			T25	6030		T26	138		T27	57
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4703878	1			T23	1		T24	765		T25	24430
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3469696	1			T24	781		T25	14849		T26	169
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1227806	1			T25	6419		T26	140		T27	54
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1568832	1			T25	9890		T27	138		T28	17
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	378436	1			T25	873		T26	122		T27	22
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1219922	1			T25	6407		T26	157		T27	35
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4700847	1			T23	1		T24	784		T25	24390
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3479208	1			T24	762		T25	14938		T26	210
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1225770	1			T25	6766		T26	120		T27	78
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1568325	1			T25	9995		T27	142		T28	14
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	380915	1			T25	802		T26	150		T27	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1213505	1			T25	5977		T26	113		T27	47
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4696907	1			T23	1		T24	753		T25	24192
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3479352	1			T24	793		T25	15047		T26	186
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1231654	1			T25	6557		T26	136		T27	60
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1569200	1			T25	10007		T27	148		T28	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	378166	1			T25	770		T26	100		T27	14
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1213291	1			T25	6295		T26	160		T27	40
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4714741	1			T23	1		T24	789		T25	24330
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3475458	1			T24	757		T25	14808		T26	203
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1226699	1			T25	6389		T26	138		T27	40
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1561851	1			T25	10096		T27	187		T28	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	376985	1			T25	772		T26	105		T27	38
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1212836	1			T25	6473		T26	142		T27	79
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4712042	1			T23	1		T24	767		T25	24530
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3473336	1			T24	779		T25	15048		T26	207
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1229835	1			T25	6555		T26	105		T27	80
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1564305	1			T25	9742		T27	114		T28	14
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	378712	1			T25	776		T26	160		T27	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1210340	1			T25	6217		T26	116		T27	64
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4698474	1			T23	1		T24	768		T25	24185
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3483566	1			T24	778		T25	14869		T26	212
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1226887	1			T25	6331		T26	126		T27	25
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1566936	1			T25	10203		T27	193		T28	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	377805	1			T25	826		T26	137		T27	37
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1214902	1			T25	6454		T26	118		T27	64
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4691686	1			T23	1		T24	777		T25	24296
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3485621	1			T24	769		T25	14921		T26	219
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1225221	1			T25	6632		T26	138		T27	83
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1572108	1			T25	9930		T27	147		T28	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	382130	1			T25	808		T26	113		T27	26
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1211804	1			T25	6281		T26	118		T27	43
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4707691	1			T23	1		T24	761		T25	24354
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3473556	1			T24	785		T25	14905		T26	177
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1220327	1			T25	6354		T26	150		T27	41
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1570710	1			T25	10053		T27	159		T28	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	381508	1			T25	804		T26	133		T27	14
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1214778	1			T25	6398		T26	118		T27	33
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4703133	1			T23	1		T24	762		T25	24696
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3479462	1			T24	784		T25	15055		T26	217
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1223147	1			T25	6525		T26	102		T27	58
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1569012	1			T25	9622		T27	118		T28	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	380194	1			T25	803		T26	166		T27	13
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1213622	1			T25	6167		T26	106		T27	42
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4702964	1			T23	1		T24	747		T25	24253
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3476470	1			T24	799		T25	14947		T26	205
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1225813	1			T25	6535		T26	124		T27	78
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1568198	1			T25	9995		T27	151		T28	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	381095	1			T25	753		T26	139		T27	26
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1214030	1			T25	6385		T26	124		T27	62
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4700527	1			T23	1		T24	784		T25	23744
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3480004	1			T24	762		T25	15007		T26	207
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1222188	1			T25	6194		T26	120		T27	79
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1568739	1			T25	10155		T27	112		T28	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	379937	1			T25	780		T26	127		T27	17
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1217175	1			T25	6988		T26	128		T27	57
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4702988	1			T23	1		T24	763		T25	24482
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3479723	1			T24	783		T25	14964		T26	194
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1228744	1			T25	6399		T26	108		T27	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1566448	1			T25	9719		T27	143		T28	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	376238	1			T25	797		T26	142		T27	15
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1214429	1			T25	6507		T26	129		T27	43
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4690682	1			T23	1		T24	771		T25	24480
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3490638	1			T24	775		T25	15046		T26	232
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1223645	1			T25	6822		T26	101		T27	93
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1568599	1			T25	9663		T27	99		T28	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	377631	1			T25	768		T26	148		T27	18
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1217375	1			T25	6089		T26	112		T27	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4692507	1			T23	1		T24	797		T25	24556
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3484153	1			T24	749		T25	14806		T26	191
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1224977	1			T25	6563		T26	140		T27	49
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1570950	1			T25	10143		T27	175		T28	12
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	381046	1			T25	774		T26	142		T27	36
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1214937	1			T25	6026		T26	121		T27	56
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4697721	1			T23	1		T24	758		T25	24083
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3484433	1			T24	788		T25	14974		T26	179
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1227274	1			T25	6231		T26	138		T27	41
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1565519	1			T25	10262		T27	164		T28	14
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	380079	1			T25	782		T26	137		T27	24
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1213544	1			T25	6536		T26	134		T27	65
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4699894	1			T23	1		T24	765		T25	24123
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3476723	1			T24	781		T25	14820		T26	221
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1225460	1			T25	6331		T26	120		T27	92
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1570776	1			T25	10119		T27	118		T28	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	377519	1			T25	803		T26	134		T27	19
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1218198	1			T25	6672		T26	121		T27	41
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4708148	1			T23	1		T24	761		T25	24698
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3474647	1			T24	785		T25	14927		T26	213
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1225600	1			T25	6107		T26	110		T27	75
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1566690	1			T25	10238		T27	168		T28	19
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	380806	1			T25	734		T26	146		T27	25
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1212679	1			T25	6164		T26	118		T27	47

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal