Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[1]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[2]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[3]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[4]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[5]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[6]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[7]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[8]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[9]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[10]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[11]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[12]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[13]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[14]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[15]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[16]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[17]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[18]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[19]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[20]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[21]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[22]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[23]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[24]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[25]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[26]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[27]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[28]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[29]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[30]	12568570	1			T23	1		T24	1546		T25	62868
bins_for_gpio_bits[31]	12568570	1			T23	1		T24	1546		T25	62868

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239790046

1

T23

32

T24

24557

T25

130645

auto[1]

162404194

1

T24

24915

T25

705321

T26

14839

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

239781429

1

T23

32

T24

24557

T25

130636

auto[1]

162412811

1

T24

24915

T25

705408

T26

14832

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7275307	1			T23	1		T24	726		T25	40114
bins_for_gpio_bits[0]	auto[0]	auto[1]	219187	1			T25	1063		T26	33		T27	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	219439	1			T25	1066		T26	33		T27	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	4854637	1			T24	820		T25	20625		T26	417
bins_for_gpio_bits[1]	auto[0]	auto[0]	7272099	1			T23	1		T24	781		T25	39939
bins_for_gpio_bits[1]	auto[0]	auto[1]	219267	1			T25	1040		T26	31		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	219550	1			T25	1043		T26	31		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	4857654	1			T24	765		T25	20846		T26	426
bins_for_gpio_bits[2]	auto[0]	auto[0]	7281102	1			T23	1		T24	758		T25	39734
bins_for_gpio_bits[2]	auto[0]	auto[1]	218460	1			T25	1047		T26	32		T27	10
bins_for_gpio_bits[2]	auto[1]	auto[0]	218752	1			T25	1050		T26	31		T27	10
bins_for_gpio_bits[2]	auto[1]	auto[1]	4850256	1			T24	788		T25	21037		T26	402
bins_for_gpio_bits[3]	auto[0]	auto[0]	7265292	1			T23	1		T24	752		T25	40003
bins_for_gpio_bits[3]	auto[0]	auto[1]	218935	1			T25	1041		T26	31		T27	8
bins_for_gpio_bits[3]	auto[1]	auto[0]	219207	1			T25	1042		T26	31		T27	8
bins_for_gpio_bits[3]	auto[1]	auto[1]	4865136	1			T24	794		T25	20782		T26	472
bins_for_gpio_bits[4]	auto[0]	auto[0]	7269038	1			T23	1		T24	768		T25	39368
bins_for_gpio_bits[4]	auto[0]	auto[1]	218768	1			T25	1098		T26	29		T27	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	219003	1			T25	1101		T26	29		T27	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	4861761	1			T24	778		T25	21301		T26	446
bins_for_gpio_bits[5]	auto[0]	auto[0]	7267060	1			T23	1		T24	778		T25	39903
bins_for_gpio_bits[5]	auto[0]	auto[1]	218642	1			T25	1021		T26	36		T27	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	218920	1			T25	1024		T26	35		T27	10
bins_for_gpio_bits[5]	auto[1]	auto[1]	4863948	1			T24	768		T25	20920		T26	423
bins_for_gpio_bits[6]	auto[0]	auto[0]	7280195	1			T23	1		T24	764		T25	40225
bins_for_gpio_bits[6]	auto[0]	auto[1]	218631	1			T25	1024		T26	31		T27	14
bins_for_gpio_bits[6]	auto[1]	auto[0]	218904	1			T25	1029		T26	30		T27	14
bins_for_gpio_bits[6]	auto[1]	auto[1]	4850840	1			T24	782		T25	20590		T26	424
bins_for_gpio_bits[7]	auto[0]	auto[0]	7271713	1			T23	1		T24	784		T25	39672
bins_for_gpio_bits[7]	auto[0]	auto[1]	218849	1			T25	1067		T26	36		T27	9
bins_for_gpio_bits[7]	auto[1]	auto[0]	219103	1			T25	1070		T26	36		T27	9
bins_for_gpio_bits[7]	auto[1]	auto[1]	4858905	1			T24	762		T25	21059		T26	425
bins_for_gpio_bits[8]	auto[0]	auto[0]	7271138	1			T23	1		T24	802		T25	39568
bins_for_gpio_bits[8]	auto[0]	auto[1]	218792	1			T25	1075		T26	31		T27	8
bins_for_gpio_bits[8]	auto[1]	auto[0]	219072	1			T25	1076		T26	30		T27	8
bins_for_gpio_bits[8]	auto[1]	auto[1]	4859568	1			T24	744		T25	21149		T26	434
bins_for_gpio_bits[9]	auto[0]	auto[0]	7274445	1			T23	1		T24	769		T25	39783
bins_for_gpio_bits[9]	auto[0]	auto[1]	218598	1			T25	1051		T26	31		T27	11
bins_for_gpio_bits[9]	auto[1]	auto[0]	218900	1			T25	1052		T26	31		T27	11
bins_for_gpio_bits[9]	auto[1]	auto[1]	4856627	1			T24	777		T25	20982		T26	413
bins_for_gpio_bits[10]	auto[0]	auto[0]	7262807	1			T23	1		T24	787		T25	39506
bins_for_gpio_bits[10]	auto[0]	auto[1]	218863	1			T25	1098		T26	36		T27	17
bins_for_gpio_bits[10]	auto[1]	auto[0]	219122	1			T25	1099		T26	35		T27	17
bins_for_gpio_bits[10]	auto[1]	auto[1]	4867778	1			T24	759		T25	21165		T26	418
bins_for_gpio_bits[11]	auto[0]	auto[0]	7266636	1			T23	1		T24	727		T25	39884
bins_for_gpio_bits[11]	auto[0]	auto[1]	218728	1			T25	1052		T26	31		T27	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	219039	1			T25	1054		T26	31		T27	16
bins_for_gpio_bits[11]	auto[1]	auto[1]	4864167	1			T24	819		T25	20878		T26	430
bins_for_gpio_bits[12]	auto[0]	auto[0]	7263916	1			T23	1		T24	737		T25	39465
bins_for_gpio_bits[12]	auto[0]	auto[1]	218991	1			T25	1101		T26	29		T27	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	219240	1			T25	1102		T26	29		T27	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	4866423	1			T24	809		T25	21200		T26	460
bins_for_gpio_bits[13]	auto[0]	auto[0]	7279752	1			T23	1		T24	776		T25	39898
bins_for_gpio_bits[13]	auto[0]	auto[1]	219212	1			T25	1034		T26	32		T27	7
bins_for_gpio_bits[13]	auto[1]	auto[0]	219454	1			T25	1035		T26	32		T27	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	4850152	1			T24	770		T25	20901		T26	445
bins_for_gpio_bits[14]	auto[0]	auto[0]	7279485	1			T23	1		T24	776		T25	40140
bins_for_gpio_bits[14]	auto[0]	auto[1]	219004	1			T25	1043		T26	28		T27	10
bins_for_gpio_bits[14]	auto[1]	auto[0]	219281	1			T25	1046		T26	28		T27	10
bins_for_gpio_bits[14]	auto[1]	auto[1]	4850800	1			T24	770		T25	20639		T26	449
bins_for_gpio_bits[15]	auto[0]	auto[0]	7281379	1			T23	1		T24	765		T25	39664
bins_for_gpio_bits[15]	auto[0]	auto[1]	218873	1			T25	1073		T26	32		T27	6
bins_for_gpio_bits[15]	auto[1]	auto[0]	219137	1			T25	1075		T26	32		T27	6
bins_for_gpio_bits[15]	auto[1]	auto[1]	4849181	1			T24	781		T25	21056		T26	416
bins_for_gpio_bits[16]	auto[0]	auto[0]	7276191	1			T23	1		T24	784		T25	40081
bins_for_gpio_bits[16]	auto[0]	auto[1]	218472	1			T25	1066		T26	36		T27	9
bins_for_gpio_bits[16]	auto[1]	auto[0]	218751	1			T25	1070		T26	36		T27	9
bins_for_gpio_bits[16]	auto[1]	auto[1]	4855156	1			T24	762		T25	20651		T26	437
bins_for_gpio_bits[17]	auto[0]	auto[0]	7278358	1			T23	1		T24	753		T25	39695
bins_for_gpio_bits[17]	auto[0]	auto[1]	219137	1			T25	1057		T26	34		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	219403	1			T25	1061		T26	34		T27	8
bins_for_gpio_bits[17]	auto[1]	auto[1]	4851672	1			T24	793		T25	21055		T26	412
bins_for_gpio_bits[18]	auto[0]	auto[0]	7284427	1			T23	1		T24	789		T25	39703
bins_for_gpio_bits[18]	auto[0]	auto[1]	218562	1			T25	1109		T26	37		T27	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	218864	1			T25	1112		T26	37		T27	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	4846717	1			T24	757		T25	20944		T26	413
bins_for_gpio_bits[19]	auto[0]	auto[0]	7287083	1			T23	1		T24	767		T25	39752
bins_for_gpio_bits[19]	auto[0]	auto[1]	218866	1			T25	1074		T26	31		T27	13
bins_for_gpio_bits[19]	auto[1]	auto[0]	219099	1			T25	1075		T26	30		T27	13
bins_for_gpio_bits[19]	auto[1]	auto[1]	4843522	1			T24	779		T25	20967		T26	452
bins_for_gpio_bits[20]	auto[0]	auto[0]	7272562	1			T23	1		T24	768		T25	39609
bins_for_gpio_bits[20]	auto[0]	auto[1]	219447	1			T25	1105		T26	31		T27	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	219735	1			T25	1110		T26	31		T27	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	4856826	1			T24	778		T25	21044		T26	436
bins_for_gpio_bits[21]	auto[0]	auto[0]	7270225	1			T23	1		T24	777		T25	39757
bins_for_gpio_bits[21]	auto[0]	auto[1]	218544	1			T25	1099		T26	33		T27	10
bins_for_gpio_bits[21]	auto[1]	auto[0]	218790	1			T25	1101		T26	33		T27	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	4861011	1			T24	769		T25	20911		T26	417
bins_for_gpio_bits[22]	auto[0]	auto[0]	7279743	1			T23	1		T24	761		T25	39656
bins_for_gpio_bits[22]	auto[0]	auto[1]	218705	1			T25	1102		T26	33		T27	6
bins_for_gpio_bits[22]	auto[1]	auto[0]	218985	1			T25	1105		T26	33		T27	6
bins_for_gpio_bits[22]	auto[1]	auto[1]	4851137	1			T24	785		T25	21005		T26	395
bins_for_gpio_bits[23]	auto[0]	auto[0]	7275943	1			T23	1		T24	762		T25	39742
bins_for_gpio_bits[23]	auto[0]	auto[1]	219072	1			T25	1096		T26	34		T27	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	219349	1			T25	1101		T26	34		T27	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	4854206	1			T24	784		T25	20929		T26	455
bins_for_gpio_bits[24]	auto[0]	auto[0]	7277937	1			T23	1		T24	747		T25	39715
bins_for_gpio_bits[24]	auto[0]	auto[1]	218745	1			T25	1065		T26	34		T27	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	219038	1			T25	1068		T26	34		T27	10
bins_for_gpio_bits[24]	auto[1]	auto[1]	4852850	1			T24	799		T25	21020		T26	434
bins_for_gpio_bits[25]	auto[0]	auto[0]	7272344	1			T23	1		T24	784		T25	38982
bins_for_gpio_bits[25]	auto[0]	auto[1]	218836	1			T25	1110		T26	33		T27	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	219110	1			T25	1111		T26	33		T27	11
bins_for_gpio_bits[25]	auto[1]	auto[1]	4858280	1			T24	762		T25	21665		T26	429
bins_for_gpio_bits[26]	auto[0]	auto[0]	7278348	1			T23	1		T24	763		T25	39512
bins_for_gpio_bits[26]	auto[0]	auto[1]	219592	1			T25	1088		T26	30		T27	8
bins_for_gpio_bits[26]	auto[1]	auto[0]	219832	1			T25	1088		T26	30		T27	8
bins_for_gpio_bits[26]	auto[1]	auto[1]	4850798	1			T24	783		T25	21180		T26	435
bins_for_gpio_bits[27]	auto[0]	auto[0]	7263678	1			T23	1		T24	771		T25	39936
bins_for_gpio_bits[27]	auto[0]	auto[1]	218979	1			T25	1025		T26	28		T27	12
bins_for_gpio_bits[27]	auto[1]	auto[0]	219248	1			T25	1029		T26	27		T27	12
bins_for_gpio_bits[27]	auto[1]	auto[1]	4866665	1			T24	775		T25	20878		T26	464
bins_for_gpio_bits[28]	auto[0]	auto[0]	7269283	1			T23	1		T24	797		T25	40198
bins_for_gpio_bits[28]	auto[0]	auto[1]	218940	1			T25	1060		T26	36		T27	8
bins_for_gpio_bits[28]	auto[1]	auto[0]	219151	1			T25	1064		T26	36		T27	8
bins_for_gpio_bits[28]	auto[1]	auto[1]	4861196	1			T24	749		T25	20546		T26	418
bins_for_gpio_bits[29]	auto[0]	auto[0]	7271068	1			T23	1		T24	758		T25	39501
bins_for_gpio_bits[29]	auto[0]	auto[1]	219184	1			T25	1071		T26	32		T27	11
bins_for_gpio_bits[29]	auto[1]	auto[0]	219446	1			T25	1075		T26	32		T27	11
bins_for_gpio_bits[29]	auto[1]	auto[1]	4858872	1			T24	788		T25	21221		T26	418
bins_for_gpio_bits[30]	auto[0]	auto[0]	7276866	1			T23	1		T24	765		T25	39463
bins_for_gpio_bits[30]	auto[0]	auto[1]	218981	1			T25	1105		T26	31		T27	9
bins_for_gpio_bits[30]	auto[1]	auto[0]	219264	1			T25	1110		T26	31		T27	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	4853459	1			T24	781		T25	21190		T26	445
bins_for_gpio_bits[31]	auto[0]	auto[0]	7281856	1			T23	1		T24	761		T25	40051
bins_for_gpio_bits[31]	auto[0]	auto[1]	218291	1			T25	989		T26	30		T27	7
bins_for_gpio_bits[31]	auto[1]	auto[0]	218582	1			T25	992		T26	30		T27	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	4849841	1			T24	785		T25	20836		T26	447