Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434976 |
1 |
|
|
T23 |
1 |
|
T24 |
817 |
|
T25 |
36584 |
| auto[1] |
5339698 |
1 |
|
|
T24 |
1241 |
|
T25 |
29294 |
|
T28 |
715 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12082057 |
1 |
|
|
T23 |
1 |
|
T24 |
1852 |
|
T25 |
62000 |
| auto[1] |
692617 |
1 |
|
|
T24 |
206 |
|
T25 |
3878 |
|
T28 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7396510 |
1 |
|
|
T23 |
1 |
|
T24 |
981 |
|
T25 |
36836 |
| auto[1] |
5378164 |
1 |
|
|
T24 |
1077 |
|
T25 |
29042 |
|
T28 |
904 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346570 |
1 |
|
|
T24 |
400 |
|
T25 |
12118 |
|
T28 |
526 |
| auto[1] |
auto[0] |
auto[1] |
346615 |
1 |
|
|
T24 |
103 |
|
T25 |
1814 |
|
T28 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2338977 |
1 |
|
|
T24 |
471 |
|
T25 |
13046 |
|
T28 |
336 |
| auto[1] |
auto[1] |
auto[1] |
346002 |
1 |
|
|
T24 |
103 |
|
T25 |
2064 |
|
T28 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7450396 |
1 |
|
|
T23 |
1 |
|
T24 |
935 |
|
T25 |
35977 |
| auto[1] |
5324278 |
1 |
|
|
T24 |
1123 |
|
T25 |
29901 |
|
T28 |
764 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12086747 |
1 |
|
|
T23 |
1 |
|
T24 |
1844 |
|
T25 |
62294 |
| auto[1] |
687927 |
1 |
|
|
T24 |
214 |
|
T25 |
3584 |
|
T28 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7430319 |
1 |
|
|
T23 |
1 |
|
T24 |
905 |
|
T25 |
37689 |
| auto[1] |
5344355 |
1 |
|
|
T24 |
1153 |
|
T25 |
28189 |
|
T28 |
937 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2326963 |
1 |
|
|
T24 |
396 |
|
T25 |
12025 |
|
T28 |
517 |
| auto[1] |
auto[0] |
auto[1] |
343839 |
1 |
|
|
T24 |
91 |
|
T25 |
1748 |
|
T28 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2329465 |
1 |
|
|
T24 |
543 |
|
T25 |
12580 |
|
T28 |
381 |
| auto[1] |
auto[1] |
auto[1] |
344088 |
1 |
|
|
T24 |
123 |
|
T25 |
1836 |
|
T28 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446705 |
1 |
|
|
T23 |
1 |
|
T24 |
846 |
|
T25 |
36127 |
| auto[1] |
5327969 |
1 |
|
|
T24 |
1212 |
|
T25 |
29751 |
|
T28 |
1160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12086631 |
1 |
|
|
T23 |
1 |
|
T24 |
1886 |
|
T25 |
62217 |
| auto[1] |
688043 |
1 |
|
|
T24 |
172 |
|
T25 |
3661 |
|
T28 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7426426 |
1 |
|
|
T23 |
1 |
|
T24 |
1159 |
|
T25 |
37527 |
| auto[1] |
5348248 |
1 |
|
|
T24 |
899 |
|
T25 |
28351 |
|
T28 |
924 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2332622 |
1 |
|
|
T24 |
332 |
|
T25 |
11856 |
|
T28 |
373 |
| auto[1] |
auto[0] |
auto[1] |
344446 |
1 |
|
|
T24 |
74 |
|
T25 |
1745 |
|
T28 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2327583 |
1 |
|
|
T24 |
395 |
|
T25 |
12834 |
|
T28 |
515 |
| auto[1] |
auto[1] |
auto[1] |
343597 |
1 |
|
|
T24 |
98 |
|
T25 |
1916 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434114 |
1 |
|
|
T23 |
1 |
|
T24 |
1574 |
|
T25 |
36308 |
| auto[1] |
5340560 |
1 |
|
|
T24 |
484 |
|
T25 |
29570 |
|
T28 |
1119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12090866 |
1 |
|
|
T23 |
1 |
|
T24 |
1917 |
|
T25 |
62174 |
| auto[1] |
683808 |
1 |
|
|
T24 |
141 |
|
T25 |
3704 |
|
T28 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452711 |
1 |
|
|
T23 |
1 |
|
T24 |
1319 |
|
T25 |
36635 |
| auto[1] |
5321963 |
1 |
|
|
T24 |
739 |
|
T25 |
29243 |
|
T28 |
1020 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2303130 |
1 |
|
|
T24 |
467 |
|
T25 |
12422 |
|
T28 |
414 |
| auto[1] |
auto[0] |
auto[1] |
339234 |
1 |
|
|
T24 |
111 |
|
T25 |
1801 |
|
T28 |
29 |
| auto[1] |
auto[1] |
auto[0] |
2335025 |
1 |
|
|
T24 |
131 |
|
T25 |
13117 |
|
T28 |
557 |
| auto[1] |
auto[1] |
auto[1] |
344574 |
1 |
|
|
T24 |
30 |
|
T25 |
1903 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439260 |
1 |
|
|
T23 |
1 |
|
T24 |
866 |
|
T25 |
36661 |
| auto[1] |
5335414 |
1 |
|
|
T24 |
1192 |
|
T25 |
29217 |
|
T28 |
1019 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12083071 |
1 |
|
|
T23 |
1 |
|
T24 |
1836 |
|
T25 |
62236 |
| auto[1] |
691603 |
1 |
|
|
T24 |
222 |
|
T25 |
3642 |
|
T28 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7398900 |
1 |
|
|
T23 |
1 |
|
T24 |
853 |
|
T25 |
37238 |
| auto[1] |
5375774 |
1 |
|
|
T24 |
1205 |
|
T25 |
28640 |
|
T28 |
1092 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2341030 |
1 |
|
|
T24 |
377 |
|
T25 |
12414 |
|
T28 |
534 |
| auto[1] |
auto[0] |
auto[1] |
345044 |
1 |
|
|
T24 |
91 |
|
T25 |
1788 |
|
T28 |
28 |
| auto[1] |
auto[1] |
auto[0] |
2343141 |
1 |
|
|
T24 |
606 |
|
T25 |
12584 |
|
T28 |
512 |
| auto[1] |
auto[1] |
auto[1] |
346559 |
1 |
|
|
T24 |
131 |
|
T25 |
1854 |
|
T28 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7458453 |
1 |
|
|
T23 |
1 |
|
T24 |
987 |
|
T25 |
38141 |
| auto[1] |
5316221 |
1 |
|
|
T24 |
1071 |
|
T25 |
27737 |
|
T28 |
1022 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12085680 |
1 |
|
|
T23 |
1 |
|
T24 |
1837 |
|
T25 |
62199 |
| auto[1] |
688994 |
1 |
|
|
T24 |
221 |
|
T25 |
3679 |
|
T28 |
45 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7421679 |
1 |
|
|
T23 |
1 |
|
T24 |
894 |
|
T25 |
37130 |
| auto[1] |
5352995 |
1 |
|
|
T24 |
1164 |
|
T25 |
28748 |
|
T28 |
990 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2325774 |
1 |
|
|
T24 |
460 |
|
T25 |
13105 |
|
T28 |
506 |
| auto[1] |
auto[0] |
auto[1] |
343958 |
1 |
|
|
T24 |
104 |
|
T25 |
1950 |
|
T28 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2338227 |
1 |
|
|
T24 |
483 |
|
T25 |
11964 |
|
T28 |
439 |
| auto[1] |
auto[1] |
auto[1] |
345036 |
1 |
|
|
T24 |
117 |
|
T25 |
1729 |
|
T28 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7432110 |
1 |
|
|
T23 |
1 |
|
T24 |
951 |
|
T25 |
36955 |
| auto[1] |
5342564 |
1 |
|
|
T24 |
1107 |
|
T25 |
28923 |
|
T28 |
934 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12088305 |
1 |
|
|
T23 |
1 |
|
T24 |
1829 |
|
T25 |
62173 |
| auto[1] |
686369 |
1 |
|
|
T24 |
229 |
|
T25 |
3705 |
|
T28 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434646 |
1 |
|
|
T23 |
1 |
|
T24 |
852 |
|
T25 |
37092 |
| auto[1] |
5340028 |
1 |
|
|
T24 |
1206 |
|
T25 |
28786 |
|
T28 |
874 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2307231 |
1 |
|
|
T24 |
485 |
|
T25 |
12646 |
|
T28 |
414 |
| auto[1] |
auto[0] |
auto[1] |
339590 |
1 |
|
|
T24 |
124 |
|
T25 |
1858 |
|
T28 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2346428 |
1 |
|
|
T24 |
492 |
|
T25 |
12435 |
|
T28 |
424 |
| auto[1] |
auto[1] |
auto[1] |
346779 |
1 |
|
|
T24 |
105 |
|
T25 |
1847 |
|
T28 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445608 |
1 |
|
|
T23 |
1 |
|
T24 |
1298 |
|
T25 |
37729 |
| auto[1] |
5329066 |
1 |
|
|
T24 |
760 |
|
T25 |
28149 |
|
T28 |
855 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12093811 |
1 |
|
|
T23 |
1 |
|
T24 |
1859 |
|
T25 |
62055 |
| auto[1] |
680863 |
1 |
|
|
T24 |
199 |
|
T25 |
3823 |
|
T28 |
39 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459758 |
1 |
|
|
T23 |
1 |
|
T24 |
985 |
|
T25 |
36063 |
| auto[1] |
5314916 |
1 |
|
|
T24 |
1073 |
|
T25 |
29815 |
|
T28 |
993 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2325383 |
1 |
|
|
T24 |
477 |
|
T25 |
13906 |
|
T28 |
558 |
| auto[1] |
auto[0] |
auto[1] |
342667 |
1 |
|
|
T24 |
107 |
|
T25 |
2133 |
|
T28 |
23 |
| auto[1] |
auto[1] |
auto[0] |
2308670 |
1 |
|
|
T24 |
397 |
|
T25 |
12086 |
|
T28 |
396 |
| auto[1] |
auto[1] |
auto[1] |
338196 |
1 |
|
|
T24 |
92 |
|
T25 |
1690 |
|
T28 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7462657 |
1 |
|
|
T23 |
1 |
|
T24 |
863 |
|
T25 |
36231 |
| auto[1] |
5312017 |
1 |
|
|
T24 |
1195 |
|
T25 |
29647 |
|
T28 |
1115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12087686 |
1 |
|
|
T23 |
1 |
|
T24 |
1794 |
|
T25 |
62126 |
| auto[1] |
686988 |
1 |
|
|
T24 |
264 |
|
T25 |
3752 |
|
T28 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435831 |
1 |
|
|
T23 |
1 |
|
T24 |
672 |
|
T25 |
36330 |
| auto[1] |
5338843 |
1 |
|
|
T24 |
1386 |
|
T25 |
29548 |
|
T28 |
1039 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2353166 |
1 |
|
|
T24 |
516 |
|
T25 |
12416 |
|
T28 |
457 |
| auto[1] |
auto[0] |
auto[1] |
347613 |
1 |
|
|
T24 |
117 |
|
T25 |
1872 |
|
T28 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2298689 |
1 |
|
|
T24 |
606 |
|
T25 |
13380 |
|
T28 |
540 |
| auto[1] |
auto[1] |
auto[1] |
339375 |
1 |
|
|
T24 |
147 |
|
T25 |
1880 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434031 |
1 |
|
|
T23 |
1 |
|
T24 |
939 |
|
T25 |
37307 |
| auto[1] |
5340643 |
1 |
|
|
T24 |
1119 |
|
T25 |
28571 |
|
T28 |
1054 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12092868 |
1 |
|
|
T23 |
1 |
|
T24 |
1874 |
|
T25 |
62365 |
| auto[1] |
681806 |
1 |
|
|
T24 |
184 |
|
T25 |
3513 |
|
T28 |
41 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460963 |
1 |
|
|
T23 |
1 |
|
T24 |
1061 |
|
T25 |
38010 |
| auto[1] |
5313711 |
1 |
|
|
T24 |
997 |
|
T25 |
27868 |
|
T28 |
1148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2319479 |
1 |
|
|
T24 |
457 |
|
T25 |
11766 |
|
T28 |
544 |
| auto[1] |
auto[0] |
auto[1] |
341429 |
1 |
|
|
T24 |
107 |
|
T25 |
1706 |
|
T28 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2312426 |
1 |
|
|
T24 |
356 |
|
T25 |
12589 |
|
T28 |
563 |
| auto[1] |
auto[1] |
auto[1] |
340377 |
1 |
|
|
T24 |
77 |
|
T25 |
1807 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447678 |
1 |
|
|
T23 |
1 |
|
T24 |
963 |
|
T25 |
37862 |
| auto[1] |
5326996 |
1 |
|
|
T24 |
1095 |
|
T25 |
28016 |
|
T28 |
1021 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12084415 |
1 |
|
|
T23 |
1 |
|
T24 |
1897 |
|
T25 |
62117 |
| auto[1] |
690259 |
1 |
|
|
T24 |
161 |
|
T25 |
3761 |
|
T28 |
29 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423379 |
1 |
|
|
T23 |
1 |
|
T24 |
1218 |
|
T25 |
37066 |
| auto[1] |
5351295 |
1 |
|
|
T24 |
840 |
|
T25 |
28812 |
|
T28 |
818 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2340755 |
1 |
|
|
T24 |
288 |
|
T25 |
13188 |
|
T28 |
315 |
| auto[1] |
auto[0] |
auto[1] |
347693 |
1 |
|
|
T24 |
70 |
|
T25 |
2002 |
|
T28 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2320281 |
1 |
|
|
T24 |
391 |
|
T25 |
11863 |
|
T28 |
474 |
| auto[1] |
auto[1] |
auto[1] |
342566 |
1 |
|
|
T24 |
91 |
|
T25 |
1759 |
|
T28 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447115 |
1 |
|
|
T23 |
1 |
|
T24 |
1150 |
|
T25 |
36546 |
| auto[1] |
5327559 |
1 |
|
|
T24 |
908 |
|
T25 |
29332 |
|
T28 |
861 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12089046 |
1 |
|
|
T23 |
1 |
|
T24 |
1870 |
|
T25 |
62009 |
| auto[1] |
685628 |
1 |
|
|
T24 |
188 |
|
T25 |
3869 |
|
T28 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439089 |
1 |
|
|
T23 |
1 |
|
T24 |
997 |
|
T25 |
36311 |
| auto[1] |
5335585 |
1 |
|
|
T24 |
1061 |
|
T25 |
29567 |
|
T28 |
786 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2336874 |
1 |
|
|
T24 |
474 |
|
T25 |
12693 |
|
T28 |
452 |
| auto[1] |
auto[0] |
auto[1] |
345385 |
1 |
|
|
T24 |
95 |
|
T25 |
1975 |
|
T28 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2313083 |
1 |
|
|
T24 |
399 |
|
T25 |
13005 |
|
T28 |
302 |
| auto[1] |
auto[1] |
auto[1] |
340243 |
1 |
|
|
T24 |
93 |
|
T25 |
1894 |
|
T28 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452184 |
1 |
|
|
T23 |
1 |
|
T24 |
912 |
|
T25 |
36680 |
| auto[1] |
5322490 |
1 |
|
|
T24 |
1146 |
|
T25 |
29198 |
|
T28 |
1007 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12085050 |
1 |
|
|
T23 |
1 |
|
T24 |
1889 |
|
T25 |
62056 |
| auto[1] |
689624 |
1 |
|
|
T24 |
169 |
|
T25 |
3822 |
|
T28 |
49 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7413406 |
1 |
|
|
T23 |
1 |
|
T24 |
1200 |
|
T25 |
37076 |
| auto[1] |
5361268 |
1 |
|
|
T24 |
858 |
|
T25 |
28802 |
|
T28 |
1138 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2346416 |
1 |
|
|
T24 |
261 |
|
T25 |
12318 |
|
T28 |
520 |
| auto[1] |
auto[0] |
auto[1] |
346583 |
1 |
|
|
T24 |
65 |
|
T25 |
1922 |
|
T28 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2325228 |
1 |
|
|
T24 |
428 |
|
T25 |
12662 |
|
T28 |
569 |
| auto[1] |
auto[1] |
auto[1] |
343041 |
1 |
|
|
T24 |
104 |
|
T25 |
1900 |
|
T28 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7428295 |
1 |
|
|
T23 |
1 |
|
T24 |
995 |
|
T25 |
36797 |
| auto[1] |
5346379 |
1 |
|
|
T24 |
1063 |
|
T25 |
29081 |
|
T28 |
999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12091915 |
1 |
|
|
T23 |
1 |
|
T24 |
1862 |
|
T25 |
62311 |
| auto[1] |
682759 |
1 |
|
|
T24 |
196 |
|
T25 |
3567 |
|
T28 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455467 |
1 |
|
|
T23 |
1 |
|
T24 |
1041 |
|
T25 |
36957 |
| auto[1] |
5319207 |
1 |
|
|
T24 |
1017 |
|
T25 |
28921 |
|
T28 |
1104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2321029 |
1 |
|
|
T24 |
356 |
|
T25 |
13038 |
|
T28 |
490 |
| auto[1] |
auto[0] |
auto[1] |
341481 |
1 |
|
|
T24 |
79 |
|
T25 |
1872 |
|
T28 |
21 |
| auto[1] |
auto[1] |
auto[0] |
2315419 |
1 |
|
|
T24 |
465 |
|
T25 |
12316 |
|
T28 |
572 |
| auto[1] |
auto[1] |
auto[1] |
341278 |
1 |
|
|
T24 |
117 |
|
T25 |
1695 |
|
T28 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7464081 |
1 |
|
|
T23 |
1 |
|
T24 |
1263 |
|
T25 |
36656 |
| auto[1] |
5310593 |
1 |
|
|
T24 |
795 |
|
T25 |
29222 |
|
T28 |
1041 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12087160 |
1 |
|
|
T23 |
1 |
|
T24 |
1852 |
|
T25 |
62422 |
| auto[1] |
687514 |
1 |
|
|
T24 |
206 |
|
T25 |
3456 |
|
T28 |
34 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7431472 |
1 |
|
|
T23 |
1 |
|
T24 |
930 |
|
T25 |
38318 |
| auto[1] |
5343202 |
1 |
|
|
T24 |
1128 |
|
T25 |
27560 |
|
T28 |
896 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2340009 |
1 |
|
|
T24 |
552 |
|
T25 |
11971 |
|
T28 |
411 |
| auto[1] |
auto[0] |
auto[1] |
346587 |
1 |
|
|
T24 |
128 |
|
T25 |
1700 |
|
T28 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2315679 |
1 |
|
|
T24 |
370 |
|
T25 |
12133 |
|
T28 |
451 |
| auto[1] |
auto[1] |
auto[1] |
340927 |
1 |
|
|
T24 |
78 |
|
T25 |
1756 |
|
T28 |
20 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7440387 |
1 |
|
|
T23 |
1 |
|
T24 |
1050 |
|
T25 |
35953 |
| auto[1] |
5334287 |
1 |
|
|
T24 |
1008 |
|
T25 |
29925 |
|
T28 |
922 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12085455 |
1 |
|
|
T23 |
1 |
|
T24 |
1870 |
|
T25 |
61998 |
| auto[1] |
689219 |
1 |
|
|
T24 |
188 |
|
T25 |
3880 |
|
T28 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7419817 |
1 |
|
|
T23 |
1 |
|
T24 |
1060 |
|
T25 |
36186 |
| auto[1] |
5354857 |
1 |
|
|
T24 |
998 |
|
T25 |
29692 |
|
T28 |
937 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2328235 |
1 |
|
|
T24 |
425 |
|
T25 |
12127 |
|
T28 |
511 |
| auto[1] |
auto[0] |
auto[1] |
343261 |
1 |
|
|
T24 |
96 |
|
T25 |
1806 |
|
T28 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2337403 |
1 |
|
|
T24 |
385 |
|
T25 |
13685 |
|
T28 |
394 |
| auto[1] |
auto[1] |
auto[1] |
345958 |
1 |
|
|
T24 |
92 |
|
T25 |
2074 |
|
T28 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7427923 |
1 |
|
|
T23 |
1 |
|
T24 |
811 |
|
T25 |
36883 |
| auto[1] |
5346751 |
1 |
|
|
T24 |
1247 |
|
T25 |
28995 |
|
T28 |
1073 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12090407 |
1 |
|
|
T23 |
1 |
|
T24 |
1940 |
|
T25 |
62237 |
| auto[1] |
684267 |
1 |
|
|
T24 |
118 |
|
T25 |
3641 |
|
T28 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7454208 |
1 |
|
|
T23 |
1 |
|
T24 |
1403 |
|
T25 |
37464 |
| auto[1] |
5320466 |
1 |
|
|
T24 |
655 |
|
T25 |
28414 |
|
T28 |
996 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2303251 |
1 |
|
|
T24 |
164 |
|
T25 |
12444 |
|
T28 |
494 |
| auto[1] |
auto[0] |
auto[1] |
338882 |
1 |
|
|
T24 |
38 |
|
T25 |
1816 |
|
T28 |
16 |
| auto[1] |
auto[1] |
auto[0] |
2332948 |
1 |
|
|
T24 |
373 |
|
T25 |
12329 |
|
T28 |
465 |
| auto[1] |
auto[1] |
auto[1] |
345385 |
1 |
|
|
T24 |
80 |
|
T25 |
1825 |
|
T28 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7441455 |
1 |
|
|
T23 |
1 |
|
T24 |
1220 |
|
T25 |
37750 |
| auto[1] |
5333219 |
1 |
|
|
T24 |
838 |
|
T25 |
28128 |
|
T28 |
968 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12087047 |
1 |
|
|
T23 |
1 |
|
T24 |
1866 |
|
T25 |
62263 |
| auto[1] |
687627 |
1 |
|
|
T24 |
192 |
|
T25 |
3615 |
|
T28 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435102 |
1 |
|
|
T23 |
1 |
|
T24 |
1085 |
|
T25 |
37499 |
| auto[1] |
5339572 |
1 |
|
|
T24 |
973 |
|
T25 |
28379 |
|
T28 |
911 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2325982 |
1 |
|
|
T24 |
522 |
|
T25 |
12662 |
|
T28 |
489 |
| auto[1] |
auto[0] |
auto[1] |
343334 |
1 |
|
|
T24 |
129 |
|
T25 |
1907 |
|
T28 |
24 |
| auto[1] |
auto[1] |
auto[0] |
2325963 |
1 |
|
|
T24 |
259 |
|
T25 |
12102 |
|
T28 |
384 |
| auto[1] |
auto[1] |
auto[1] |
344293 |
1 |
|
|
T24 |
63 |
|
T25 |
1708 |
|
T28 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7437042 |
1 |
|
|
T23 |
1 |
|
T24 |
892 |
|
T25 |
37423 |
| auto[1] |
5337632 |
1 |
|
|
T24 |
1166 |
|
T25 |
28455 |
|
T28 |
1074 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12091607 |
1 |
|
|
T23 |
1 |
|
T24 |
1873 |
|
T25 |
62169 |
| auto[1] |
683067 |
1 |
|
|
T24 |
185 |
|
T25 |
3709 |
|
T28 |
46 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7452919 |
1 |
|
|
T23 |
1 |
|
T24 |
1066 |
|
T25 |
36705 |
| auto[1] |
5321755 |
1 |
|
|
T24 |
992 |
|
T25 |
29173 |
|
T28 |
1015 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2333653 |
1 |
|
|
T24 |
306 |
|
T25 |
12952 |
|
T28 |
453 |
| auto[1] |
auto[0] |
auto[1] |
343725 |
1 |
|
|
T24 |
78 |
|
T25 |
1907 |
|
T28 |
17 |
| auto[1] |
auto[1] |
auto[0] |
2305035 |
1 |
|
|
T24 |
501 |
|
T25 |
12512 |
|
T28 |
516 |
| auto[1] |
auto[1] |
auto[1] |
339342 |
1 |
|
|
T24 |
107 |
|
T25 |
1802 |
|
T28 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7423373 |
1 |
|
|
T23 |
1 |
|
T24 |
945 |
|
T25 |
36504 |
| auto[1] |
5351301 |
1 |
|
|
T24 |
1113 |
|
T25 |
29374 |
|
T28 |
1017 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12087039 |
1 |
|
|
T23 |
1 |
|
T24 |
1894 |
|
T25 |
62200 |
| auto[1] |
687635 |
1 |
|
|
T24 |
164 |
|
T25 |
3678 |
|
T28 |
53 |