Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7437751 |
1 |
|
|
T23 |
1 |
|
T24 |
1044 |
|
T25 |
36550 |
| auto[1] |
5336923 |
1 |
|
|
T24 |
1014 |
|
T25 |
29328 |
|
T28 |
1152 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12091609 |
1 |
|
|
T23 |
1 |
|
T24 |
1871 |
|
T25 |
62026 |
| auto[1] |
683065 |
1 |
|
|
T24 |
187 |
|
T25 |
3852 |
|
T28 |
36 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7456063 |
1 |
|
|
T23 |
1 |
|
T24 |
1053 |
|
T25 |
36806 |
| auto[1] |
5318611 |
1 |
|
|
T24 |
1005 |
|
T25 |
29072 |
|
T28 |
880 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2324411 |
1 |
|
|
T24 |
477 |
|
T25 |
12500 |
|
T28 |
346 |
| auto[1] |
auto[0] |
auto[1] |
343345 |
1 |
|
|
T24 |
114 |
|
T25 |
1950 |
|
T28 |
19 |
| auto[1] |
auto[1] |
auto[0] |
2311135 |
1 |
|
|
T24 |
341 |
|
T25 |
12720 |
|
T28 |
498 |
| auto[1] |
auto[1] |
auto[1] |
339720 |
1 |
|
|
T24 |
73 |
|
T25 |
1902 |
|
T28 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |