Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7459339 |
1 |
|
|
T23 |
1 |
|
T24 |
846 |
|
T25 |
36505 |
| auto[1] |
5315335 |
1 |
|
|
T24 |
1212 |
|
T25 |
29373 |
|
T28 |
957 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12084808 |
1 |
|
|
T23 |
1 |
|
T24 |
1850 |
|
T25 |
62124 |
| auto[1] |
689866 |
1 |
|
|
T24 |
208 |
|
T25 |
3754 |
|
T28 |
28 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7414921 |
1 |
|
|
T23 |
1 |
|
T24 |
971 |
|
T25 |
36248 |
| auto[1] |
5359753 |
1 |
|
|
T24 |
1087 |
|
T25 |
29630 |
|
T28 |
837 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2339901 |
1 |
|
|
T24 |
430 |
|
T25 |
12391 |
|
T28 |
432 |
| auto[1] |
auto[0] |
auto[1] |
346205 |
1 |
|
|
T24 |
108 |
|
T25 |
1820 |
|
T28 |
15 |
| auto[1] |
auto[1] |
auto[0] |
2329986 |
1 |
|
|
T24 |
449 |
|
T25 |
13485 |
|
T28 |
377 |
| auto[1] |
auto[1] |
auto[1] |
343661 |
1 |
|
|
T24 |
100 |
|
T25 |
1934 |
|
T28 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |