Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7446705 |
1 |
|
|
T23 |
1 |
|
T24 |
846 |
|
T25 |
36127 |
| auto[1] |
5327969 |
1 |
|
|
T24 |
1212 |
|
T25 |
29751 |
|
T28 |
1160 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10579754 |
1 |
|
|
T23 |
1 |
|
T24 |
1581 |
|
T25 |
54418 |
| auto[1] |
2194920 |
1 |
|
|
T24 |
477 |
|
T25 |
11460 |
|
T28 |
889 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7453376 |
1 |
|
|
T23 |
1 |
|
T24 |
1019 |
|
T25 |
36604 |
| auto[1] |
5321298 |
1 |
|
|
T24 |
1039 |
|
T25 |
29274 |
|
T28 |
1141 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1573088 |
1 |
|
|
T24 |
267 |
|
T25 |
8600 |
|
T28 |
109 |
| auto[1] |
auto[0] |
auto[1] |
1106911 |
1 |
|
|
T24 |
227 |
|
T25 |
5519 |
|
T28 |
364 |
| auto[1] |
auto[1] |
auto[0] |
1553290 |
1 |
|
|
T24 |
295 |
|
T25 |
9214 |
|
T28 |
143 |
| auto[1] |
auto[1] |
auto[1] |
1088009 |
1 |
|
|
T24 |
250 |
|
T25 |
5941 |
|
T28 |
525 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |