Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434114 |
1 |
|
|
T23 |
1 |
|
T24 |
1574 |
|
T25 |
36308 |
| auto[1] |
5340560 |
1 |
|
|
T24 |
484 |
|
T25 |
29570 |
|
T28 |
1119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10564445 |
1 |
|
|
T23 |
1 |
|
T24 |
1369 |
|
T25 |
54235 |
| auto[1] |
2210229 |
1 |
|
|
T24 |
689 |
|
T25 |
11643 |
|
T28 |
621 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7409814 |
1 |
|
|
T23 |
1 |
|
T24 |
771 |
|
T25 |
36350 |
| auto[1] |
5364860 |
1 |
|
|
T24 |
1287 |
|
T25 |
29528 |
|
T28 |
851 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1580866 |
1 |
|
|
T24 |
485 |
|
T25 |
8720 |
|
T28 |
70 |
| auto[1] |
auto[0] |
auto[1] |
1107983 |
1 |
|
|
T24 |
561 |
|
T25 |
5881 |
|
T28 |
253 |
| auto[1] |
auto[1] |
auto[0] |
1573765 |
1 |
|
|
T24 |
113 |
|
T25 |
9165 |
|
T28 |
160 |
| auto[1] |
auto[1] |
auto[1] |
1102246 |
1 |
|
|
T24 |
128 |
|
T25 |
5762 |
|
T28 |
368 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |