Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7439260 |
1 |
|
|
T23 |
1 |
|
T24 |
866 |
|
T25 |
36661 |
| auto[1] |
5335414 |
1 |
|
|
T24 |
1192 |
|
T25 |
29217 |
|
T28 |
1019 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10572949 |
1 |
|
|
T23 |
1 |
|
T24 |
1531 |
|
T25 |
54503 |
| auto[1] |
2201725 |
1 |
|
|
T24 |
527 |
|
T25 |
11375 |
|
T28 |
883 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7427137 |
1 |
|
|
T23 |
1 |
|
T24 |
1083 |
|
T25 |
37328 |
| auto[1] |
5347537 |
1 |
|
|
T24 |
975 |
|
T25 |
28550 |
|
T28 |
1214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1567439 |
1 |
|
|
T24 |
164 |
|
T25 |
8507 |
|
T28 |
179 |
| auto[1] |
auto[0] |
auto[1] |
1097562 |
1 |
|
|
T24 |
176 |
|
T25 |
5617 |
|
T28 |
465 |
| auto[1] |
auto[1] |
auto[0] |
1578373 |
1 |
|
|
T24 |
284 |
|
T25 |
8668 |
|
T28 |
152 |
| auto[1] |
auto[1] |
auto[1] |
1104163 |
1 |
|
|
T24 |
351 |
|
T25 |
5758 |
|
T28 |
418 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |