Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7428536 |
1 |
|
|
T23 |
1 |
|
T24 |
1138 |
|
T25 |
37196 |
| auto[1] |
5346138 |
1 |
|
|
T24 |
920 |
|
T25 |
28682 |
|
T28 |
991 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2321892 |
1 |
|
|
T24 |
418 |
|
T25 |
12260 |
|
T28 |
493 |
| auto[1] |
auto[0] |
auto[1] |
341652 |
1 |
|
|
T24 |
93 |
|
T25 |
1728 |
|
T28 |
32 |
| auto[1] |
auto[1] |
auto[0] |
2336611 |
1 |
|
|
T24 |
338 |
|
T25 |
12744 |
|
T28 |
445 |
| auto[1] |
auto[1] |
auto[1] |
345983 |
1 |
|
|
T24 |
71 |
|
T25 |
1950 |
|
T28 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |