Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7432110 |
1 |
|
|
T23 |
1 |
|
T24 |
951 |
|
T25 |
36955 |
auto[1] |
5342564 |
1 |
|
|
T24 |
1107 |
|
T25 |
28923 |
|
T28 |
934 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10584319 |
1 |
|
|
T23 |
1 |
|
T24 |
1564 |
|
T25 |
54280 |
auto[1] |
2190355 |
1 |
|
|
T24 |
494 |
|
T25 |
11598 |
|
T28 |
739 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7463576 |
1 |
|
|
T23 |
1 |
|
T24 |
1060 |
|
T25 |
36701 |
auto[1] |
5311098 |
1 |
|
|
T24 |
998 |
|
T25 |
29177 |
|
T28 |
981 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
1563860 |
1 |
|
|
T24 |
273 |
|
T25 |
8781 |
|
T28 |
141 |
auto[1] |
auto[0] |
auto[1] |
1096816 |
1 |
|
|
T24 |
241 |
|
T25 |
5660 |
|
T28 |
414 |
auto[1] |
auto[1] |
auto[0] |
1556883 |
1 |
|
|
T24 |
231 |
|
T25 |
8798 |
|
T28 |
101 |
auto[1] |
auto[1] |
auto[1] |
1093539 |
1 |
|
|
T24 |
253 |
|
T25 |
5938 |
|
T28 |
325 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |