Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7434031 |
1 |
|
|
T23 |
1 |
|
T24 |
939 |
|
T25 |
37307 |
| auto[1] |
5340643 |
1 |
|
|
T24 |
1119 |
|
T25 |
28571 |
|
T28 |
1054 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10588689 |
1 |
|
|
T23 |
1 |
|
T24 |
1564 |
|
T25 |
53674 |
| auto[1] |
2185985 |
1 |
|
|
T24 |
494 |
|
T25 |
12204 |
|
T28 |
739 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7475632 |
1 |
|
|
T23 |
1 |
|
T24 |
1084 |
|
T25 |
36283 |
| auto[1] |
5299042 |
1 |
|
|
T24 |
974 |
|
T25 |
29595 |
|
T28 |
980 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1557543 |
1 |
|
|
T24 |
182 |
|
T25 |
8780 |
|
T28 |
100 |
| auto[1] |
auto[0] |
auto[1] |
1093142 |
1 |
|
|
T24 |
195 |
|
T25 |
6250 |
|
T28 |
348 |
| auto[1] |
auto[1] |
auto[0] |
1555514 |
1 |
|
|
T24 |
298 |
|
T25 |
8611 |
|
T28 |
141 |
| auto[1] |
auto[1] |
auto[1] |
1092843 |
1 |
|
|
T24 |
299 |
|
T25 |
5954 |
|
T28 |
391 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |