Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447678 |
1 |
|
|
T23 |
1 |
|
T24 |
963 |
|
T25 |
37862 |
| auto[1] |
5326996 |
1 |
|
|
T24 |
1095 |
|
T25 |
28016 |
|
T28 |
1021 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10580308 |
1 |
|
|
T23 |
1 |
|
T24 |
1440 |
|
T25 |
54446 |
| auto[1] |
2194366 |
1 |
|
|
T24 |
618 |
|
T25 |
11432 |
|
T28 |
785 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7455279 |
1 |
|
|
T23 |
1 |
|
T24 |
851 |
|
T25 |
36912 |
| auto[1] |
5319395 |
1 |
|
|
T24 |
1207 |
|
T25 |
28966 |
|
T28 |
976 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1559100 |
1 |
|
|
T24 |
269 |
|
T25 |
9452 |
|
T28 |
138 |
| auto[1] |
auto[0] |
auto[1] |
1101690 |
1 |
|
|
T24 |
252 |
|
T25 |
6091 |
|
T28 |
349 |
| auto[1] |
auto[1] |
auto[0] |
1565929 |
1 |
|
|
T24 |
320 |
|
T25 |
8082 |
|
T28 |
53 |
| auto[1] |
auto[1] |
auto[1] |
1092676 |
1 |
|
|
T24 |
366 |
|
T25 |
5341 |
|
T28 |
436 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |