Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7428295 |
1 |
|
|
T23 |
1 |
|
T24 |
995 |
|
T25 |
36797 |
| auto[1] |
5346379 |
1 |
|
|
T24 |
1063 |
|
T25 |
29081 |
|
T28 |
999 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10586977 |
1 |
|
|
T23 |
1 |
|
T24 |
1402 |
|
T25 |
54228 |
| auto[1] |
2187697 |
1 |
|
|
T24 |
656 |
|
T25 |
11650 |
|
T28 |
972 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7460234 |
1 |
|
|
T23 |
1 |
|
T24 |
712 |
|
T25 |
36781 |
| auto[1] |
5314440 |
1 |
|
|
T24 |
1346 |
|
T25 |
29097 |
|
T28 |
1148 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1551368 |
1 |
|
|
T24 |
361 |
|
T25 |
8634 |
|
T28 |
111 |
| auto[1] |
auto[0] |
auto[1] |
1090529 |
1 |
|
|
T24 |
346 |
|
T25 |
5820 |
|
T28 |
541 |
| auto[1] |
auto[1] |
auto[0] |
1575375 |
1 |
|
|
T24 |
329 |
|
T25 |
8813 |
|
T28 |
65 |
| auto[1] |
auto[1] |
auto[1] |
1097168 |
1 |
|
|
T24 |
310 |
|
T25 |
5830 |
|
T28 |
431 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |