Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7464081 |
1 |
|
|
T23 |
1 |
|
T24 |
1263 |
|
T25 |
36656 |
| auto[1] |
5310593 |
1 |
|
|
T24 |
795 |
|
T25 |
29222 |
|
T28 |
1041 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10579534 |
1 |
|
|
T23 |
1 |
|
T24 |
1681 |
|
T25 |
54298 |
| auto[1] |
2195140 |
1 |
|
|
T24 |
377 |
|
T25 |
11580 |
|
T28 |
784 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7457321 |
1 |
|
|
T23 |
1 |
|
T24 |
1272 |
|
T25 |
37105 |
| auto[1] |
5317353 |
1 |
|
|
T24 |
786 |
|
T25 |
28773 |
|
T28 |
1010 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1567741 |
1 |
|
|
T24 |
288 |
|
T25 |
8612 |
|
T28 |
77 |
| auto[1] |
auto[0] |
auto[1] |
1104262 |
1 |
|
|
T24 |
262 |
|
T25 |
5853 |
|
T28 |
444 |
| auto[1] |
auto[1] |
auto[0] |
1554472 |
1 |
|
|
T24 |
121 |
|
T25 |
8581 |
|
T28 |
149 |
| auto[1] |
auto[1] |
auto[1] |
1090878 |
1 |
|
|
T24 |
115 |
|
T25 |
5727 |
|
T28 |
340 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |