Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7447294 |
1 |
|
|
T23 |
1 |
|
T24 |
1205 |
|
T25 |
35589 |
| auto[1] |
5327380 |
1 |
|
|
T24 |
853 |
|
T25 |
30289 |
|
T28 |
945 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12088887 |
1 |
|
|
T23 |
1 |
|
T24 |
1839 |
|
T25 |
62170 |
| auto[1] |
685787 |
1 |
|
|
T24 |
219 |
|
T25 |
3708 |
|
T28 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7435177 |
1 |
|
|
T23 |
1 |
|
T24 |
920 |
|
T25 |
36691 |
| auto[1] |
5339497 |
1 |
|
|
T24 |
1138 |
|
T25 |
29187 |
|
T28 |
1002 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2326459 |
1 |
|
|
T24 |
537 |
|
T25 |
11875 |
|
T28 |
468 |
| auto[1] |
auto[0] |
auto[1] |
343273 |
1 |
|
|
T24 |
122 |
|
T25 |
1695 |
|
T28 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2327251 |
1 |
|
|
T24 |
382 |
|
T25 |
13604 |
|
T28 |
492 |
| auto[1] |
auto[1] |
auto[1] |
342514 |
1 |
|
|
T24 |
97 |
|
T25 |
2013 |
|
T28 |
22 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |